This paper introduces a 10T single-ended SRAM cell with high stability and low static power. The read static noise margin is augmented by using a Schmitt-trigger inverter and decoupling the storage node from the read bitline by adding one transistor. Since writing “1” is difficult in single-ended SRAM cells, using proper capacitive coupling and also extra pMOS transistor as an access transistor mitigates the problem. To evaluate read, write, and hold yields, we performed 10,000 Monto Carlo simulations in the 32-nm technology, and the results show our cell has 7.5×, 1.4×, and 1.1 × more yields than that of the conventional 6T SRAM cell. The proposed cell also has the least static power consumption. This amount is 1.5× less than the conventional 6T at the supply voltage of 0.5 V.

本文介绍了一种具有高稳定性和低静态功耗的10T单端SRAM单元。通过使用施密特触发器反相器并通过添加一个晶体管将存储节点与读取位线去耦，可以提高读取静态噪声容限。由于在单端SRAM单元中很难写入“ 1”，因此使用适当的电容耦合以及额外的pMOS晶体管作为访问晶体管可以缓解该问题。为了评估读取，写入和保持的良率，我们在32纳米技术中进行了10,000次Monto Carlo模拟，结果表明我们的单元比传统6T SRAM单元的良率高7.5倍，1.4倍和1.1倍。所提出的单元还具有最小的静态功耗。在0.5 V的电源电压下，此数量比传统的6T小1.5倍。