Bias Temperature Instability and soft error rate are the major reliability issue with the technology scaling. BTI leads to an increase in the threshold voltage of the MOS transistors, which reduces the drain current. The threshold voltage of the PMOS transistor increases due to NBTI with stress time, which degrades the circuit performance. In this paper, we propose a novel reliable voltage bootstrapped Schmitt trigger circuit with soft error hardening enhancement and lower effect of BTI. We investigate all the circuit simulations which impact on the soft error rate of inverter circuits using HSPICE 65 nm CMOS technology. The results show that the proposed inverter circuit has a higher critical charge and lower soft error rate (SER) when compared to other reference inverter circuits. To better assess, we introduced V_th sensitivity and observed that the degradation of the proposed inverter circuit is 30% higher as compared to conventional CMOS inverter. The proposed inverter offers lower dynamic power, leakage power, and circuit delay of 91.11%, 93.47%, and 38.17%, respectively, as compared to CMOS inverter at 3 years of the stress time. Finally, the overall circuit performance is evaluated using the figure of merits and observes that the proposed inverter has the highest FOM correspond to other inverter circuits, which reveal that the proposed circuit is useful for the applications where the effect of radiations are higher.

偏置温度不稳定性和软错误率是技术扩展中主要的可靠性问题。BTI导致MOS晶体管的阈值电压增加，从而降低了漏极电流。由于NBTI的作用，PMOS晶体管的阈值电压随应力时间而增加，这会降低电路性能。在本文中，我们提出了一种新颖的，可靠的电压自举施密特触发器电路，该电路具有软错误强化增强功能和较低的BTI效应。我们研究了所有使用HSPICE 65 nm CMOS技术影响逆变器电路软错误率的电路仿真。结果表明，与其他参考逆变器电路相比，该逆变器电路具有更高的临界电荷和更低的软错误率（SER）。为了更好地评估，我们引入了V _th并观察到，与传统的CMOS反相器相比，拟议的反相器电路的劣化要高30％。与在应力时间为3年的CMOS逆变器相比，与CMOS逆变器相比，拟议的逆变器可提供更低的动态功率，泄漏功率和电路延迟，分别为91.11％，93.47％和38.17％。最后，使用优值图评估整体电路性能，并观察到拟议的逆变器具有最高的FOM，其对应于其他逆变器电路，这表明拟议的电路可用于辐射效应较高的应用。