The approximate design has emerged as a revolutionary design paradigm to obtain energy efficient digital signal processing cores while exhibiting acceptable accuracy. In different signal processing architectures, multiplier is the prime arithmetic unit and significantly influences the performance of these cores. Therefore, four novel energy efficient rounding based approximate (RBA) multiplier architectures are proposed in this paper. These multipliers first approximate input operands to the nearest power of two values and then achieve multiplication using few adders and shifters. The proposed RBA multipliers significantly reduce implementation complexity and provide higher energy efficiency. Further, a novel reconfigurable rounding based approximate (RRBA) multiplier is proposed to achieve desired performance-quality tradeoff. Further, the performance of proposed RBA and RRBA multipliers is evaluated and analysed over the existing approximate multiplier architectures. The proposed 8-bit RBA0 requires 59.8% (54.7%) reduced area (delay) compared to the existing approximate multiplier. Finally, the efficacy of the proposed multipliers is demonstrated in the application by implementing Gaussian filters embedded with existing and proposed approximate multipliers. The Gaussian filter designed using RBA0 provides 32.5% reduced energy consumption over the filter with existing multiplier.

近似设计已成为一种革命性的设计范例，可在获得可接受的精度的同时获得高能效的数字信号处理内核。在不同的信号处理架构中，乘法器是主要的运算单元，并且会显着影响这些内核的性能。因此，本文提出了四种新颖的基于能效舍入的近似（RBA）乘法器体系结构。这些乘法器首先将输入操作数近似为两个值的最接近幂，然后使用很少的加法器和移位器实现乘法。拟议的RBA乘数显着降低了实现复杂性并提供了更高的能源效率。此外，提出了一种新颖的基于可重构的舍入近似（RRBA）乘法器，以实现所需的性能质量折衷。进一步，在现有的近似乘法器体系结构上评估和分析了建议的RBA和RRBA乘法器的性能。与现有的近似乘法器相比，拟议的8位RBA0需要减少59.8％（54.7％）的面积（延迟）。最后，通过实施嵌入现有和拟议的近似乘法器的高斯滤波器，在应用中证明了拟议的乘法器的功效。与现有乘法器相比，使用RBA0设计的高斯滤波器可将能耗降低32.5％。通过实施嵌入现有和拟议的近似乘法器的高斯滤波器，在应用中证明了拟议的乘法器的功效。与现有乘法器相比，使用RBA0设计的高斯滤波器可将能耗降低32.5％。通过实施嵌入现有和拟议的近似乘法器的高斯滤波器，在应用中证明了拟议的乘法器的功效。与现有乘法器相比，使用RBA0设计的高斯滤波器可将能耗降低32.5％。