This article presents a CMOS-based, code-domain (CD), full-duplex (FD) transceiver operating in a link at 1 GHz. The CD FD link rejects in-band transmitter self-interference (TX SI) by more than 100 dB through a combination of pseudo-noise (PN) code orthogonality, circulator, and digital cancellation algorithms. A nonmagnetic CMOS circulator based on switched transmission lines is used as an antenna interface with >40-dB maximum rejection. Then, transmitter (TX) and receiver (RX) modulators spread the TX SI and correlate the desired RX signal in the RF domain. Orthogonality between the PN codes allows an additional >40-dB maximum rejection relaxing the FD transceiver linearity requirements. Finally, digital self-interference cancellation (SIC) eliminates any residual TX SI in the digital domain using a least mean squares (LMS) estimation for the SI channel based on a nonlinear truncated Volterra series model. The digital SIC can have almost 40 dB of rejection depending on the SI power level. An implemented FD node leverages these techniques to achieve an overall rejection that is around 104 dB bringing the TX signal from 20 dBm to the noise floor of the RX at −85 dBm.

中文翻译：

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具有大于 100dB 抑制的码域、带内、全双工无线通信链路

本文介绍了一种在 1 GHz 链路中运行的基于 CMOS 的码域 (CD) 全双工 (FD) 收发器。CD FD 链路通过伪噪声 (PN) 码正交性、循环器和数字消除算法的组合，将带内发射机自干扰 (TX SI) 抑制了 100 dB 以上。基于开关传输线的非磁性 CMOS 环行器用作天线接口，最大抑制 >40-dB。然后，发射器 (TX) 和接收器 (RX) 调制器扩展 TX SI 并关联 RF 域中所需的 RX 信号。PN 码之间的正交性允许额外的 >40-dB 最大抑制，从而放宽 FD 收发器线性度要求。最后，数字自干扰消除 (SIC) 使用基于非线性截断 Volterra 级数模型的 SI 信道的最小均方 (LMS) 估计来消除数字域中的任何残余 TX SI。取决于 SI 功率电平，数字 SIC 可以具有近 40 dB 的抑制。已实现的 FD 节点利用这些技术实现大约 104 dB 的总体抑制，将 TX 信号从 20 dBm 带到 -85 dBm 的 RX 噪底。