This article presents a four-element 7.5–9-GHz phased-array receiver with 1–8 concurrent beams in a 65-nm CMOS technology. Each output beam utilizes all the input elements to maximize the beamforming gain. To realize a low-power and compact design, the multielement multibeam phased-array architecture features the gm-based variable-gain phase shifter (VG-PS) and the current-sharing active combiner. The VG-PS with 6-bit phase resolution achieves <2° root mean square (rms) phase error and <0.3 dB rms gain error at the maximum gain setting. The receiver demonstrates a 20-dB power gain, a 3.6-dB noise figure (NF), and a −19-dBm input 1-dB gain compression point (IP1dB) at 7.5–9 GHz for each element. The chip occupies $5.42\times3.62$ mm2 area excluding pads and consumes 860 mW, equivalent to the record low 27 mW per element per beam. To our knowledge, the receiver achieves the maximum number of simultaneously reconfigurable beams with the lowest power consumption per element per beam in RF phase shifting and combining receiver chips.

中文翻译：

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在 65-nm CMOS 中具有 1-8 个同时可重构波束的四元件 7.5-9-GHz 相控阵接收器

本文介绍了一种采用 65 纳米 CMOS 技术的具有 1-8 个并发光束的四元件 7.5-9-GHz 相控阵接收器。每个输出光束利用所有输入元件来最大化波束形成增益。为实现低功耗和紧凑设计，多单元多波束相控阵架构采用基于 gm 的可变增益移相器 (VG-PS) 和均流有源组合器。具有 6 位相位分辨率的 VG-PS 在最大增益设置下实现 <2° 均方根 (rms) 相位误差和 <0.3 dB rms 增益误差。接收器在 7.5–9 GHz 处为每个元件展示了 20-dB 功率增益、3.6-dB 噪声系数 (NF) 和 -19-dBm 输入 1-dB 增益压缩点 (IP1dB)。该芯片占用 5.42 美元\乘以 3.62 美元 mm2 的面积，不包括焊盘，功耗为 860 mW，相当于每光束每元件 27 mW 的最低功耗。