U-channel ultra-thin body and buried oxide (U-UTBB) Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) present unique features which are simple, high-performance, area efficient, and compatible with CMOS technology. In this paper, we present the electrical characteristics of a U-UTBB SOI MOSFET with reforming the U-channel. This proposed symmetrical and planar device is initiated by removing two spacers around the recessed metal gate in the U-channel MOSFET. Hence, it causes to increase the overall channel length at the firm metal gate space along with saving area. As it has confirmed by two-dimensional and two-carrier device simulation results, the proposed structure which is termed Reformed U-UTBB (R-U-UTBB) fully depleted SOI MOSFET exhibits advantages in the device performance focusing on short channel effects (SCEs) factors including the sub-threshold slope, the drain induced barrier lowering (DIBL), and the threshold voltage roll-off. Leakage current and on-to-off current ratio are studied as well which all of them show the superiority of proposed structure compared with the U-UTBB FD SOI MOSFET and a conventional UTBB (C-UTBB) FD SOI MOSFET. In addition, the effects of process-induced variations have investigated by varying buried oxide thickness, top silicon thickness, channel thickness, substrate doping, and oxide thickness on threshold voltage, sub-threshold slope, and drain induced barrier lowering (DIBL).

U沟道超薄体和掩埋氧化物（U-UTBB）绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）具有简单，高性能，高效且与CMOS技术兼容的独特功能。在本文中，我们介绍了通过重塑U沟道的U-UTBB SOI MOSFET的电气特性。通过移除U沟道MOSFET中凹入的金属栅极周围的两个间隔物，可以启动这种建议的对称平面器件。因此，这导致增加了牢固的金属栅极空间处的总沟道长度以及节省的面积。二维和双载流子器件仿真结果已经证实，所提出的被称为改革U-UTBB（RU-UTBB）完全耗尽SOI MOSFET的结构在器件性能方面表现出优势，重点在于短沟道效应（SCE）因素，包括亚阈值斜率，漏极引起的势垒降低（DIBL），和阈值电压下降。还研究了漏电流和通断电流比，它们均显示出与U-UTBB FD SOI MOSFET和常规UTBB（C-UTBB）FD SOI MOSFET相比，所提出结构的优越性。此外，通过改变掩埋氧化物厚度，顶部硅厚度，沟道厚度，衬底掺杂和氧化物厚度对阈值电压，亚阈值斜率和漏极引起的势垒降低（DIBL）的影响，研究了工艺引起的变化的影响。漏极引起的势垒降低（DIBL）和阈值电压下降。还研究了漏电流和通断电流比，它们均显示出与U-UTBB FD SOI MOSFET和常规UTBB（C-UTBB）FD SOI MOSFET相比，所提出结构的优越性。此外，通过改变掩埋氧化物厚度，顶部硅厚度，沟道厚度，衬底掺杂和氧化物厚度对阈值电压，亚阈值斜率和漏极引起的势垒降低（DIBL）的影响，研究了工艺引起的变化的影响。漏极引起的势垒降低（DIBL）和阈值电压下降。还研究了漏电流和通断电流比，它们均显示出与U-UTBB FD SOI MOSFET和常规UTBB（C-UTBB）FD SOI MOSFET相比，所提出结构的优越性。此外，通过改变掩埋氧化物厚度，顶部硅厚度，沟道厚度，衬底掺杂和氧化物厚度对阈值电压，亚阈值斜率和漏极引起的势垒降低（DIBL）的影响，研究了工艺引起的变化的影响。