The main topic of this paper is low-cost public key cryptography in wireless sensor nodes. Security in embedded systems, for example, in sensor nodes based on field programmable gate array (FPGA), demands low cost but still efficient solutions. Sensor nodes are key elements in the Internet of Things paradigm, and their security is a crucial requirement for critical applications in sectors such as military, health, and industry. To address these security requirements under the restrictions imposed by the available computing resources of sensor nodes, this paper presents a low-area FPGA-prototyped hardware accelerator for scalar multiplication, the most costly operation in elliptic curve cryptography (ECC). This cryptoengine is provided as an enabler of robust cryptography for security services in the IoT, such as confidentiality and authentication. The compact property in the proposed hardware design is achieved by implementing a novel digit-by-digit computing approach applied at the finite field and curve level algorithms, in addition to hardware reusing, the use of embedded memory blocks in modern FPGAs, and a simpler control logic. Our hardware design targets elliptic curves defined over binary fields generated by trinomials, uses fewer area resources than other FPGA approaches, and is faster than software counterparts. Our ECC hardware accelerator was validated under a hardware/software codesign of the Diffie-Hellman key exchange protocol (ECDH) deployed in the IoT MicroZed FPGA board. For a scalar multiplication in the sect233 curve, our design requires 1170 FPGA slices and completes the computation in 128820 clock cycles (at 135.31 MHz), with an efficiency of 0.209 kbps/slice. In the codesign, the ECDH protocol is executed in 4.1 ms, 17 times faster than a MIRACL software implementation running on the embedded processor Cortex A9 in the MicroZed. The FPGA-based accelerator for binary ECC presented in this work is the one with the least amount of hardware resources compared to other FPGA designs in the literature.

中文翻译：

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用于无线传感器网络中基于曲线的密码学的基于FPGA的紧凑型加速器

本文的主要主题是无线传感器节点中的低成本公钥加密。嵌入式系统（例如，基于现场可编程门阵列（FPGA）的传感器节点）中的安全性需要低成本但仍高效的解决方案。传感器节点是物联网范式中的关键元素，其安全性是军事，卫生和工业等部门关键应用程序的关键要求。为了在传感器节点的可用计算资源所施加的限制下满足这些安全要求，本文提出了一种用于标量乘法的低面积FPGA原型硬件加速器，它是椭圆曲线密码术（ECC）中最昂贵的运算。提供此加密引擎是用于IoT中安全服务（例如机密性和身份验证）的鲁棒加密技术的实现器。所提出的硬件设计的紧凑特性是通过实施一种新颖的逐位计算方法来实现的，该方法适用于有限域和曲线级算法，此外还可以重复使用硬件，在现代FPGA中使用嵌入式存储模块以及更简单的方法。控制逻辑。我们的硬件设计目标是在由三项式生成的二进制字段上定义的椭圆曲线，与其他FPGA方法相比使用更少的区域资源，并且比软件同行更快。我们的ECC硬件加速器已通过IoT MicroZed FPGA板上部署的Diffie-Hellman密钥交换协议（ECDH）的硬件/软件代码签名进行了验证。对于标量乘法 我们的硬件设计目标是在由三项式生成的二进制字段上定义的椭圆曲线，与其他FPGA方法相比使用更少的区域资源，并且比软件同行更快。我们的ECC硬件加速器已通过IoT MicroZed FPGA板上部署的Diffie-Hellman密钥交换协议（ECDH）的硬件/软件代码签名进行了验证。对于标量乘法 我们的硬件设计目标是在由三项式生成的二进制字段上定义的椭圆曲线，与其他FPGA方法相比使用更少的区域资源，并且比软件同行更快。我们的ECC硬件加速器已通过IoT MicroZed FPGA板上部署的Diffie-Hellman密钥交换协议（ECDH）的硬件/软件代码签名进行了验证。对于标量乘法sect233曲线，我们的设计需要1170个FPGA切片，并在128820个时钟周期（在135.31 MHz下）完成计算，效率为0.209 kbps /切片。在代码符号中，ECDH协议的执行时间为4.1毫秒，比MicroZed中嵌入式处理器Cortex A9上运行的MIRACL软件实现快17倍。与文献中的其他FPGA设计相比，本文中介绍的基于FPGA的二进制ECC加速器是硬件资源最少的加速器。