Introducing the reconfigurability concept into one of the most ramping and trending design platforms like the NoC is considered a good opportunity for gaining the most out of them. The high flexibility and full customization of the reconfigurable NoC could open the door for a completely adaptive NoC that suits a large number of benchmarks according to runtime needs and requirements.

The main objective of this work is to present the Dynamic Partial Reconfiguration (DPR) support to CONNECT Network-on-Chip (NoC) for Field Programmable Gate Array (FPGA) applications. It also analyzes the effect of this reconfigurability on the performance of the network and how reconfigurability could lead to area and power saving. Reconfigurability during runtime leads to more flexible NoCs and enables full customization for dynamic reconfigurable applications. In comparison with static NoCs, dynamically reconfigurable NoCs achieve more area utilization by reusing a part of the network area resources when it is not required during runtime. A reconfiguration tool is developed helping the designer to decide the optimal network structure for every application used. The reconfiguration tool requires as inputs the minimum needed throughput and the expected traffic load. Those inputs are used to decide the best network configuration and the minimum area that achieves those requirements.

将可重新配置性概念引入诸如NoC之类的最流行，最流行的设计平台之一被认为是一个从中获得最大收益的好机会。可重配置NoC的高度灵活性和完全自定义功能可以为完全适应性NoC打开大门，该NoC可根据运行时需求和要求适应大量基准。

这项工作的主要目的是为现场可编程门阵列（FPGA）应用提供对CONNECT片上网络（NoC）的动态部分重配置（DPR）支持。它还分析了这种可重新配置性对网络性能的影响，以及可重新配置性如何导致面积和省电。运行时期间的可重新配置性带来了更灵活的NoC，并为动态可重新配置的应用程序实现了完全自定义。与静态NoC相比，动态重配置的NoC在运行时不需要时通过重用部分网络区域资源来提高区域利用率。开发了一种重新配置工具，可帮助设计人员确定所用每种应用的最佳网络结构。重新配置工具需要输入所需的最小吞吐量和预期的流量负载。这些输入用于确定最佳的网络配置和可满足这些要求的最小区域。