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Approximate Karatsuba multiplier for error-resilient applications
AEU - International Journal of Electronics and Communications ( IF 3.2 ) Pub Date : 2021-01-05 , DOI: 10.1016/j.aeue.2020.153579
Riya Jain , Neeta Pandey

Approximate computing is one of the most trending topics for research since the introduction of error-resilient applications. Approximate arithmetic helps reduce the power consumption, hardware utilization and delay time at the expense of accuracy. Out of all arithmetic operations, multiplication is the most widely used and it forms the crucial section in many applications. Therefore, it is necessary to optimize it as per the requirement of a system. This paper proposes an algorithm for approximate multiplication based on Karatsuba multiplication method which is compared with an existing approximate hybrid Wallace tree multiplier and it is found that the proposed approximate Karatsuba multiplier is better than existing approximate hybrid Wallace Tree multiplier in terms of hardware, latency as well as accuracy. The performance of proposed multiplier is also evaluated with the help of a application of image processing and it is found that proposed multiplier gives similar results as exact multiplier unit. Both the multipliers are implemented in Verilog HDL using Vivado 2018.3.



中文翻译:

近似Karatsuba乘法器,可用于错误恢复应用

自从引入抗错误的应用程序以来,近似计算是研究中最热门的主题之一。近似算法有助于降低功耗,硬件利用率和延迟时间,但会降低精度。在所有算术运算中,乘法是使用最广泛的方法,它构成了许多应用程序中的关键部分。因此,有必要根据系统要求对其进行优化。提出了一种基于Karatsuba乘法的近似乘法算法,并与现有的近似混合华莱士树乘法器进行了比较,发现在硬件,等待时间等方面,提出的近似Karatsuba乘法器要优于现有的近似混合华莱士树乘法器。以及准确性。还借助于图像处理的应用来评估所提出的乘法器的性能,并且发现所提出的乘法器给出与精确乘法器单元相似的结果。这两个乘数均使用Vivado 2018.3在Verilog HDL中实现。

更新日期:2021-01-10
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