The present CMOS VLSI technology is facing some challenges like working in nano scale, device density, power dissipation, operating frequency, fast execution, which demands a proper alternative. Quantum dot Cellular Automata (QCA) is one of the feasible substitutes for the same. In QCA, clocking is the primary driving source of power, and the flow of information occurs with the effect of underlying clocking circuitry. But in most of the designs, the proper use of the underlying clocking circuit was circumvented and targeted on random, ineffective clocking, which is a concern of convolution in terms of buildability. On the other hand, wire crossing plays a very critical role in cell layout, as well as the underlying clocking circuit for QCA. In this regard, a proposal for an efficient clocking scheme is of paramount importance with a reduction in underlying wire crossing. This article presents an efficient, scalable clocking scheme with a regular clocking region, feedback path, and fabricatable with minimal underlying wire crossing structure. The reduction in wire crossing significantly decreases the trouble of assembling the circuit in practice. To advocate the superiority of the proposed clocking scheme, both the combinational and the sequential design has been investigated using the proposed clocking scheme. QCADesigner is used to comply with the functionality and compared for improvement with the design in previously available clocking schemes.

当前的CMOS VLSI技术面临着一些挑战，例如以纳米规模工作，器件密度，功耗，工作频率，快速执行，这需要适当的替代方法。量子点元胞自动机（QCA）是其可行的替代品之一。在QCA中，时钟是主要的动力来源，信息流是在底层时钟电路的作用下发生的。但是在大多数设计中，都规避了对底层时钟电路的正确使用，并针对了随机，无效的时钟，这在可构建性方面是一个令人担忧的问题。另一方面，导线交叉在单元布局以及QCA的基础时钟电路中起着至关重要的作用。在这方面，提出一种有效的时钟方案的提案至关重要，因为它可以减少底层导线的交叉。本文提出了一种有效的，可扩展的时钟方案，该方案具有规则的时钟区域，反馈路径，并且可通过最少的底层导线交叉结构进行制造。实际上，导线交叉的减少大大减少了组装电路的麻烦。为了提倡所提出的时钟方案的优越性，已经使用所提出的时钟方案研究了组合设计和顺序设计。QCADesigner用于遵守功能，并在以前可用的时钟方案中与设计进行了比较以进行改进。并且可制造的底层导线交叉结构最少。实际上，导线交叉的减少大大减少了组装电路的麻烦。为了提倡所提出的时钟方案的优越性，已经使用所提出的时钟方案研究了组合设计和顺序设计。QCADesigner用于遵守功能，并在以前可用的时钟方案中与设计进行了比较以进行改进。并且可制造的底层导线交叉结构最少。实际上，导线交叉的减少大大减少了组装电路的麻烦。为了提倡所提出的时钟方案的优越性，已经使用所提出的时钟方案研究了组合设计和顺序设计。QCADesigner用于遵守功能，并在以前可用的时钟方案中与设计进行了比较以进行改进。