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Performance analysis for reliable nanoscaled FinFET logic circuits
Analog Integrated Circuits and Signal Processing ( IF 1.4 ) Pub Date : 2021-01-03 , DOI: 10.1007/s10470-020-01765-z
Umayia Mushtaq , Vijay Kumar Sharma

In the process of continuous miniaturization of devices, it is necessary to look for new devices which overcome the drawbacks of non-scalability and higher static power of metal oxide semiconductor field effect transistor (MOSFET). Fin-shaped field effect transistor (FinFET) is an important device which uses the concept of multi-gates and it is not only scalable but also dissipate lower power at lower technology nodes. This paper designs a low leakage input dependent (INDEP) approach for FinFET devices at 16 nm technology node. Numbers of logic gates are designed and simulated with the help of MOSFET and FinFET devices. Simulation results are compared by calculating the important parameters like leakage power, delay and power delay product (PDP). The designed low leakage INDEP approach is compared with the leakage control transistor (LECTOR) technique. Simulation results for different logic circuits show the large reduction in leakage power in case of FinFET logic gates as compared to MOSFET devices and more leakage saving in case of INDEP approach as compared to conventional as well as LECTOR technique. Reliability in terms of process, voltage and temperature (PVT) variations is checked by running the Monte-Carlo simulations for 1000 samples and observed that INDEP circuits are more reliable.



中文翻译:

可靠的纳米级FinFET逻辑电路的性能分析

在器件的连续小型化过程中,有必要寻找克服金属氧化物半导体场效应晶体管(MOSFET)的不可缩放性和较高静态功率的缺点的新器件。鳍形场效应晶体管(FinFET)是使用多栅极概念的重要器件,不仅具有可扩展性,而且在较低技术节点上的功耗更低。本文为16纳米技术节点的FinFET器件设计了一种低泄漏输入相关(INDEP)方法。借助MOSFET和FinFET器件,可以设计和仿真许多逻辑门。通过计算重要参数(如漏电功率,延迟和功率延迟乘积(PDP))对仿真结果进行比较。将设计的低泄漏INDEP方法与泄漏控制晶体管(LECTOR)技术进行了比较。不同逻辑电路的仿真结果表明,与MOSFET器件相比,使用FinFET逻辑门时,泄漏功率大大降低,而使用INDEP方法时,与传统以及LECTOR技术相比,泄漏功率节省更多。通过对1000个样品进行蒙特卡洛仿真,检查了工艺,电压和温度(PVT)变化的可靠性,并观察到INDEP电路更可靠。

更新日期:2021-01-03
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