In low power VLSI circuit designs, power dissipation is one of the challenging issues which is associated with threshold voltage. The reduction of threshold voltage increases the subthreshold leakage current by increasing the leakage power dissipation which plays an important role in total power dissipation. Due to this leakage power issue, the devices which are operated by battery for a long time in standby mode drained out as soon. To mitigate this problem Static Random-Access Memory (SRAM) is designed with dual control stacked inverter which exploits dual control signals. The proposed dual control stacked inverter reduces the power consumption by 43.42%, 71.71% 63.83% and reduces the delay by 77.05%, 77.06%, 77.16% when compared to sleepy stack approach, sleepy keeper approach and dual stack power gating. Similarly, the proposed dual controlled stacking SRAM with low Vth reduces the power consumption by 96.7%, 95.36%, 96.69% and 33.54% when compared to the sleepy stacky approach, sleepy keeper approach, dual stack approach and dual controlled stacking. The proposed SRAM cell increases the reliability of overall System on Chip.

在低功率VLSI电路设计中，功耗是与阈值电压相关的挑战性问题之一。阈值电压的降低通过增加泄漏功耗来增加亚阈值泄漏电流，这在总功耗中起着重要作用。由于此泄漏功率问题，由电池在待机模式下长时间运行的设备很快就会耗尽。为了缓解这个问题，静态随机存取存储器（SRAM）设计有采用双控制信号的双控制堆叠逆变器。与困堆方法，困守者方法和双堆电源选通相比，拟议的双控制堆叠逆变器可将功耗降低43.42％，71.71％63.83％，并将延迟降低77.05％，77.06％，77.16％。同样，与睡眠堆叠方法，睡眠守门员方法，双重堆叠方法和双重控制堆叠相比，建议的低Vth双控制堆叠SRAM降低了96.7％，95.36％，96.69％和33.54％的功耗。拟议的SRAM单元提高了整个片上系统的可靠性。