Time difference amplifier (TDA) is often used in time domain interconnection, computing and measurement. Gain and linearity control are two main design issues. To reduce the nonlinear distortion, a novel self-adaptive pulse shrink circuit is proposed for the SR-latch based time difference amplifier. The multi-stage self-adaptive pulse shrink unit can compensate for the gain error caused by the high-order items and decrease the linearity problem. A programmable gain control circuit is also proposed to improve the gain range of the TDA. The proposed TDA including gain reconfiguration and linearity control is implemented by using SMIC 40nm CMOS technology. Post layout simulation demonstrates that the proposed TDA achieves from 8 to 100 s/s programmable gain within the input linear range \([-36\,\hbox {ps},36\,\hbox {ps}]\). The total area is \(21.186\,\upmu \hbox {m} \times 18.435\,\upmu \hbox {m}\). The total power consumption is \(31.45\,\upmu \hbox {W}\) when the gain is 10 and the toggle frequency is 100 MHz.

时差放大器（TDA）通常用于时域互连，计算和测量。增益和线性控制是两个主要的设计问题。为了减少非线性失真，针对基于SR锁存的时差放大器，提出了一种新型的自适应脉冲收缩电路。多级自适应脉冲收缩单元可以补偿由高阶项引起的增益误差，减少线性问题。还提出了可编程增益控制电路以改善TDA的增益范围。所建议的TDA包括增益重新配置和线性控制，是通过使用SMIC 40nm CMOS技术实现的。布局后仿真表明，建议的TDA在输入线性范围内可实现8至100  s / s的可编程增益\（[-36 \，\ hbox {ps}，36 \，\ hbox {ps}] \）。总面积为\（21.186 \，\ upmu \ hbox {m} \ times 18.435 \，\ upmu \ hbox {m} \）。当增益为10且触发频率为100 MHz时，总功耗为\（31.45 \，\ upmu \ hbox {W} \）。