In this paper, a one-to-one comparison of the logic performance is made between CMOS circuits built with bulk junctionless (JL) FinFETs and that with SOI JL FinFETs for three different technology nodes as per the ITRS roadmap. For such comparison: (i) the rise time and fall time are evaluated from the transient analysis of a CMOS inverter,(ii) the propagation delay per stage for a three-stage ring oscillator is estimated from its frequency of oscillation, and (iii) the static noise margin of a 6 T SRAM cell is evaluated from its butterfly plot. A three-dimensional numerical device and mixed-mode circuit simulator is used for the performance estimation. CMOS circuits implemented with bulk JL devices are found to have comparable logic performance with their SOI JL counterparts.

在本文中，根据ITRS路线图，针对使用三种不同技术节点的，采用体无接点（JL）FinFET的CMOS电路与采用SOI JL FinFET的CMOS电路进行了逻辑性能的一对一比较。为了进行这种比较：（i）通过CMOS反相器的瞬态分析评估上升时间和下降时间;（ii）从三级环形振荡器的振荡频率估算每级的传播延迟;以及（iii ）根据其蝶形图评估6 T SRAM单元的静态噪声容限。三维数值设备和混合模式电路模拟器用于性能评估。发现使用批量JL器件实现的CMOS电路具有与SOI JL同类产品相当的逻辑性能。