ABSTRACT

The coordinate rotation digital computer (CORDIC) is a class of shift-add algorithm for the rotation of vectors on a plane. The major problem in this CORDIC algorithm is the linear rate of convergence with the speed of the iteration. The main aim of the improved CORDIC algorithm is to utilise an integrated adder subtractor in place of binary adder subtractor to decrease the count of iterations and hardware reduction technique. The improved CORDIC splits the rotation angle into several series of micro-rotation angles to calculate the rotation and the new set of angle provides a fast convergence. The canonical signed-digit (CSD) approach together with Hcub algorithm employs for the number of adder subtractor reduction and shifters in CORDIC architecture design. The performances of the proposed CORDIC design have been verified by employing it in FFT implementation. The simulation result indicates the higher frequency of 77.20%, 82.78%, 78.30% and 76.57% when compared with conventional methods. The evaluation of FFT is also done by comparing with the conventional methods. The power consumption, number of iterations and the hardware complexity reduced by using the improved CORDIC and the working of this proposed algorithm is evaluated through the FPGA implementation.

摘要

坐标旋转数字计算机（CORDIC）是一类用于平面上矢量旋转的移位相加算法。该 CORDIC 算法的主要问题是收敛速度与迭代速度的线性关系。改进的 CORDIC 算法的主要目的是利用集成的加法减法器代替二进制加法减法器来减少迭代次数和硬件缩减技术。改进后的 CORDIC 将旋转角度拆分为若干系列的微旋转角度来计算旋转，新的一组角度提供了快速收敛。规范有符号数字 (CSD) 方法与 Hcub 算法一起用于 CORDIC 架构设计中的加法器减法器减少和移位器的数量。所提出的 CORDIC 设计的性能已经通过在 FFT 实现中使用它得到了验证。仿真结果表明，与传统方法相比，频率分别提高了 77.20%、82.78%、78.30% 和 76.57%。FFT的评价也是通过与传统方法的比较来完成的。使用改进的 CORDIC 降低了功耗、迭代次数和硬件复杂度，并通过 FPGA 实现评估了该算法的工作效率。