This article presents a multiprotocol DSP-DAC-based SerDes architecture. The lookup table (LUT)-based DSP provides flexible number of taps for equalization, and soft switching driver allows 1.2-Vpp transmit swing to achieve higher SNR. The architecture employs cascaded phase-locked loop (PLL)-based flexible clocking to support a wide range of data rates from 10 to 112 Gb/s. The $LC$ PLL generates 10.25–14.5 GHz but distributes a divided version of the clock between 2.25 and 3.625 GHz with less than 140-fs integrated jitter. The local ring PLL multiplies the clock to 28 GHz but keeps the jitter less than 180 fs thanks to wide loop bandwidth. The transmitter is implemented in 7-nm FinFET consuming 175 mW with 1.56-pJ/bit efficiency.

中文翻译：

---

具有 Flex 时钟架构的 7 纳米 FinFET 中基于 10 至 112 Gb/s DSP-DAC 的发送器

本文介绍了一种基于多协议 DSP-DAC 的 SerDes 架构。基于查找表 (LUT) 的 DSP 提供灵活的均衡抽头数量，软开关驱动器允许 1.2-Vpp 发射摆幅以实现更高的 SNR。该架构采用基于级联锁相环 (PLL) 的灵活时钟来支持从 10 到 112 Gb/s 的广泛数据速率。$LC$ PLL 产生 10.25–14.5 GHz 的频率，但在 2.25 到 3.625 GHz 之间分配时钟的分频版本，集成抖动小于 140-fs。由于环路带宽较宽，本地环 PLL 将时钟倍频至 28 GHz，但将抖动保持在 180 fs 以下。发射器采用 7 纳米 FinFET 实现，功耗为 175 mW，效率为 1.56 pJ/位。