The IBM z15 system improves upon the prior-generation z14 design within the same chip footprint and technology node, while featuring the addition of two cores, 33%/100%/43% additional L2/L3/L4 cache, as well as additional core features and on-chip accelerators. The largest 5-drawer system configuration includes 20 central processor (CP) chips, five system controller (SC) chips, and 40 TB of memory. With ~200 cores across all CP chips operating with 99.99999% uptime at 5.2 GHz, z15 achieves a 25% increase in system capacity and a 14% single thread performance improvement over the z14 system. In this article, we describe the key design factors and system/characterization refinement that enabled these results, including the novel 2-Mb embedded dynamic random access memory (eDRAM) cell, a new voltage droop monitor, a more comprehensive power reduction infrastructure to reduce power-limited yield, results on reliability-limited versus power-limited yield, and a characterization effort for exploring even higher frequencies, with our first reported 6-GHz values achieved in the lab at customer temperatures and voltages.

中文翻译：

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内核、缓存、内容和特性：IBM 的第二代 14 纳米产品 z15

IBM z15 系统在相同的芯片尺寸和技术节点内改进了上一代 z14 设计，同时增加了两个内核、33%/100%/43% 的额外 L2/L3/L4 缓存以及额外的内核功能和片上加速器。最大的 5 抽屉系统配置包括 20 个中央处理器 (CP) 芯片、5 个系统控制器 (SC) 芯片和 40 TB 内存。凭借所有 CP 芯片的约 200 个内核，在 5.2 GHz 下以 99.99999% 的正常运行时间运行，z15 与 z14 系统相比，系统容量增加了 25%，单线程性能提高了 14%。在本文中，我们描述了实现这些结果的关键设计因素和系统/特性改进，包括新颖的 2 Mb 嵌入式动态随机存取存储器 (eDRAM) 单元、新的电压下降监视器、