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P-GaN Tri-Gate MOS Structure for Normally-Off GaN Power Transistors
IEEE Electron Device Letters ( IF 4.9 ) Pub Date : 2020-11-10 , DOI: 10.1109/led.2020.3037026
Minghua Zhu , Catherine Erine , Jun Ma , Mohammad Samizadeh Nikoo , Luca Nela , Pirouz Sohi , Elison Matioli

In this letter, we present a new concept for normally-off AlGaN/GaN-on-Si MOS-HEMTs based on the combination of p-GaN, tri-gate and MOS structures to achieve high threshold voltage ( ${V}_{\text {TH}}$ ) and low on-resistance ( ${R}_{ {ON}}$ ). The p-GaN is used to engineer the band structure and reduce the carrier density ( ${N}_{\text {s}}$ ) in the tri-gate structure for a high ${V}_{\text {TH}}$ . The gate control is mainly achieved from field-effect through the tri-gate sidewalls, and does not rely on injection of gate current. The MOS structure enables much larger gate voltages ( ${V}_{\text {G}}$ ) and the effective sidewall modulation results in excellent switching performance at high switching frequencies. In addition, this concept eliminates the need for thin barriers (typical in p-GaN devices), which combined to the conduction channels formed at the tri-gate sidewalls, resulted in a smaller ${R}_{ {ON}}$ compared with planar p-GaN structures. The p-GaN length and tri-gate filling factor ( FF ) were optimized to achieve a good trade-off between high ${V}_{\text {TH}}$ and low ${R}_{ {ON}}$ . The excellent channel control capability offered by the tri-gate structure led to a higher ON/OFF ratio and smaller sub-threshold slope ( SS ) compared to similar planar p-GaN devices. These results unveil the excellent prospects of p-GaN tri-gate MOS technology for future power electronics applications.

中文翻译:

用于常关型GaN功率晶体管的P-GaN三栅极MOS结构

在这封信中,我们基于p-GaN,三栅和MOS结构的组合提出了常关型AlGaN / Si-on MOS-HEMT的新概念,以实现高阈值电压( $ {V} _ {\ text {TH}} $ )和低导通电阻( $ {R} _ {{ON}} $ )。p-GaN用于设计能带结构并降低载流子密度( $ {N} _ {\ text {s}} $ )在高三闸结构中 $ {V} _ {\ text {TH}} $ 。栅极控制主要是通过三栅极侧壁的场效应实现的,并且不依赖于栅极电流的注入。MOS结构可实现更大的栅极电压( $ {V} _ {\ text {G}} $ )和有效的侧壁调制可在高开关频率下实现出色的开关性能。此外,该概念消除了对薄势垒(通常在p-GaN器件中使用)的需求,该势垒与在三栅侧壁处形成的导电沟道相结合,从而减小了尺寸 $ {R} _ {{ON}} $ 与平面p-GaN结构相比。p-GaN长度和三栅极填充因子( FF )进行了优化,以在高 $ {V} _ {\ text {TH}} $ 和低 $ {R} _ {{ON}} $ 。三栅极结构提供的出色的通道控制能力导致更高的开/关比和更小的亚阈值斜率( SS )与类似的平面p-GaN器件相比。这些结果揭示了p-GaN三栅MOS技术在未来电力电子应用中的广阔前景。
更新日期:2020-12-25
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