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A 0.7 pJ/bit, 1.5 Gbps Energy-Efficient Image-Based True Random Number Generator
IETE Journal of Research ( IF 1.5 ) Pub Date : 2020-12-22 , DOI: 10.1080/03772063.2020.1859957
Dhirendra Kumar 1 , Lakshmi Likhitha Mankali 1 , Prasanna Kumar Misra 1 , Manish Goswami 1
Affiliation  

ABSTRACT

Random numbers cover a vast spectrum of applications. Hence generating it effectively with high performance is the need of the hour. This paper presents the novel design and implementation of high performance and energy-efficient true random number generator (TRNG) using images as a source. In the proposed work, the harvesting mechanism that comprises of hashing technique block (HTB) is used to reduce the intensity of pattern, an event counting circuit (ECC) is used for comparing the events, while a linear feedback shift register (LFSR), designed by considering a primitive polynomial function, is used to obtain the random numbers. The addition of 8 × 1 multiplexer (MUX) with meta-stable circuit feeder control lines had further increased the unpredictability in the proposed system. The implementation of the work has been done in the Xilinx Vivado simulation tool followed by the Cadence Virtuoso circuit simulation environment. The maximum speed of 1.5 Gbps with power dissipation of 1 mW and 0.7 pJ/bit energy efficiency with a layout area of 2218 μm2 has been achieved in this work. NIST 800.22 statistical test suite and uniformity test comprising of Kolmogorov–Smirnov and Chi-square test have also been performed for validation of generated random numbers. The obtained binary sequences have passed all tests successfully with calculated entropy up to 0.999999999. The autocorrelation factor (ACF) of the output bit streams has been obtained as approximately zero (∼0) within 96% confidence bounds of a Gaussian distribution (µ = 0, 3σ). The proposed design is thus suitable for true random number generation.



中文翻译:

0.7 pJ/bit、1.5 Gbps 高能效、基于图像的真随机数发生器

摘要

随机数涵盖了广泛的应用。因此,迫切需要以高性能有效地生成它。本文介绍了使用图像作为源的高性能和节能真随机数生成器 (TRNG) 的新颖设计和实现。在拟议的工作中,包括哈希技术块(HTB)的收获机制用于降低模式的强度,事件计数电路(ECC)用于比较事件,而线性反馈移位寄存器(LFSR),通过考虑原始多项式函数设计,用于获取随机数。添加具有亚稳态电路馈线控制线的 8 × 1 多路复用器 (MUX) 进一步增加了拟议系统的不可预测性。该工作的实施已在 Xilinx Vivado 仿真工具中完成,随后是 Cadence Virtuoso 电路仿真环境。最大速度为 1.5 Gbps,功耗为 1 mW,能效为 0.7 pJ/bit,布局面积为 2218 μm2在这项工作中取得了成就。还执行了 NIST 800.22 统计测试套件和由 Kolmogorov–Smirnov 和卡方检验组成的均匀性测试,以验证生成的随机数。获得的二进制序列已成功通过所有测试,计算出的熵高达 0.999999999。输出比特流的自相关因子 (ACF) 在高斯分布 ( µ = 0, 3σ)的 96% 置信区间内近似为零 (∼0)  。因此,所提出的设计适用于真正的随机数生成。

更新日期:2020-12-22
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