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FPGA implementation of digital 3-D image skeletonization algorithm for shape matching applications
International Journal of Electronics ( IF 1.3 ) Pub Date : 2021-01-31 , DOI: 10.1080/00207217.2020.1859143
Perumalla Srinivasa Rao 1 , Kamatham Yedukondalu 1 , Racha Ganesh 1
Affiliation  

ABSTRACT

Image skeletonisation plays an important role in applications such as object identification, object’s shape description, pattern recognition, computer vision, telemedicine, and image compression. In this paper, an architecture is developed for the extraction of a skeleton for the 3-D greyscale object. The algorithm used in this paper is an extension of the 2-D greyscale skeletonisation algorithm presented in the literature. The skeleton of a 3-D greyscale object is extracted by using the boundary peeling off method. The skeletonisation algorithms are computationally intensive and difficult to achieve requirements in real-time. Field Programmable Gate Arrays (FPGAs) are selected for implementation so the real-time requirements are met. The proposed architecture is implemented on Virtex-5 FPGA and tested for an 8 × 8 x 3 greyscale object. Resource utilisation of FPGA and timing performance are investigated and are encouraging.



中文翻译:

用于形状匹配应用的数字 3-D 图像骨架化算法的 FPGA 实现

摘要

图像骨架化在对象识别、对象形状描述、模式识别、计算机视觉、远程医疗和图像压缩等应用中起着重要作用。在本文中,开发了一种用于提取 3-D 灰度对象骨架的架构。本文中使用的算法是文献中提出的二维灰度骨架化算法的扩展。使用边界剥离方法提取3-D灰度对象的骨架。骨架化算法计算量大,难以实时满足要求。选择现场可编程门阵列 (FPGA) 进行实施,以满足实时要求。建议的架构在 Virtex-5 FPGA 上实现,并针对8 × 8 × 3灰度对象。对 FPGA 的资源利用和时序性能进行了调查,结果令人鼓舞。

更新日期:2021-01-31
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