This paper presents a 32 Gb/s 16-level pulse amplitude modulation (PAM-16) source-series-terminated transmitter (TX) and a receiver (RX) analog front-end (AFE) in 28 nm FDSOI. The 8-way time-interleaved successive-approximation register (SAR) analog-to-digital-converter (ADC) in the RX AFE has an embedded 2-tap analog feed-forward equalizer. The design objective is to optimize the energy efficiency for the target data rate and the moderate-loss channel. For this purpose, the optimum modulation order that has the least ISI sensitivity for the given equalization capability is decided with a modeling study. All the equalization is performed in the analog domain to avoid the circuit complexity and power consumption disadvantages of the digital equalization in the selected high-order modulation. Thanks to the spectral efficiency of PAM-16 and the analog-only equalization, the figure-of-merit is improved significantly. Post-layout simulations show that the TX consumes 26.85 mW while the RX AFE consumes 49.36 mW at 32 Gb/s with PAM-16, which corresponds to 2.38 pJ/bit for the whole system.

本文介绍了一种在28 nm FDSOI中的32 Gb / s 16级脉冲幅度调制（PAM-16）源串联终端发送器（TX）和接收器（RX）模拟前端（AFE）。RX AFE中的8路时间交织逐次逼近寄存器（SAR）模数转换器（ADC）具有嵌入式2抽头模拟前馈均衡器。设计目标是针对目标数据速率和中等损耗通道优化能效。为此，通过模型研究确定对于给定的均衡能力具有最小ISI灵敏度的最佳调制阶数。所有均衡均在模拟域中执行，以避免在选定的高阶调制中进行数字均衡的电路复杂性和功耗缺点。借助PAM-16的频谱效率和仅模拟均衡功能，可显着改善品质因数。布局后仿真显示，使用PAM-16，TX功耗为26.85 mW，而RX AFE功耗为32 Gb / s时为49.36 mW，相当于整个系统2.38 pJ / bit。