A single event transient (SET) filtering technique for non-volatile field programmable gate arrays (FPGAs) are investigated experimentally using the AND-OR-Multiplexer SET filter technique. The technique combines AND – OR gate circuits in parallel with a two input multiplexer to provide a single circuit that can dissipate SETs irrespective of whether the input state is high or low. This paper presents the results of the experimental investigation, with the SET filter applied to various sequential circuit configurations in a commercial Flash-based FPGA, the 0.13-μm ProASIC3E product family (A3PE), by proton beam irradiation. Their implementation and evaluation in-beam show their efficiency in eliminating SETs and single event upsets (SEU) compared to unmitigated designs.

中文翻译：

---

新的单事件瞬态缓解技术的质子束验证

非易失性现场可编程门阵列 (FPGA) 的单事件瞬态 (SET) 滤波技术使用 AND-OR-Multiplexer SET 滤波器技术进行了实验研究。该技术将 AND – OR 门电路与两个输入多路复用器并联组合在一起，以提供单个电路，无论输入状态是高还是低，都可以耗散 SET。本文介绍了实验研究的结果，SET 滤波器通过质子束照射应用于基于闪存的商用 FPGA（0.13 微米 ProASIC3E 产品系列 (A3PE)）中的各种时序电路配置。与未缓解的设计相比，它们的实施和光束内评估显示了它们在消除 SET 和单事件翻转 (SEU) 方面的效率。