Purpose

This paper aims to present a single-block memory-based FFT processor design with a conflict-free addressing scheme for field-programmable gate arrays FPGAs with dual-port block memories. This study aims for a single-block dual-port memory-based N-point radix-2 FFT design that uses memory locations and spending minimum clock cycle.

Design/methodology/approach

A new memory-based Fast Fourier Transform (FFT) design that uses a dual-port memory block is proposed. Dual-port memory allows the design to perform two memory reads and writes in a single clock cycle. This approach achieves low operational clock and smallest memory simultaneously, excluding some small overhead for exceptional address changes. The methodology is to read from while writing to a memory location, eliminating the need for excess memory and additional clock cycles.

Findings

With the minimum memory size and the simplest architecture, radix-2 FFT and single-memory block are used. The number of clock pulses spent for all FFT operations does not provide much advantage for low-point FFT operations but is important for high-point FFT operations. With the developed algorithm, N memory is used, and the number of clock pulses spent for all FFT stages is (N/2 +1)log2N for all FFT operations.

Originality/value

This is an original paper, which has simultaneously in whole or in part been submitted anywhere else.

中文翻译：

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一种新的基于单组双端口存储器的基 2 FFT 寻址算法

目的

本文旨在为具有双端口块存储器的现场可编程门阵列 FPGA 提供一种具有无冲突寻址方案的基于单块存储器的 FFT 处理器设计。本研究旨在实现基于单块双端口存储器的 N 点基 2 FFT 设计，该设计使用存储器位置并花费最少的时钟周期。

设计/方法/方法

提出了一种新的基于存储器的快速傅立叶变换 (FFT) 设计，该设计使用双端口存储器块。双端口存储器允许设计在单个时钟周期内执行两次存储器读取和写入。这种方法同时实现了低操作时钟和最小内存，排除了一些特殊地址更改的小开销。该方法是在写入内存位置的同时读取，消除了对多余内存和额外时钟周期的需要。

发现

以最小的内存大小和最简单的架构，使用基数 2 FFT 和单内存块。用于所有 FFT 运算的时钟脉冲数对低点 FFT 运算没有太大优势，但对高点 FFT 运算很重要。使用所开发的算法，使用N 个内存，并且所有 FFT 运算用于所有 FFT 阶段的时钟脉冲数为 (N/2 +1)log2N。

原创性/价值

这是一篇原创论文，同时全部或部分提交到其他任何地方。