This article proposes a numerical solution approach and Field Programmable Gate Array implementation of a delayed fractional-order system. The proposed method is amenable to a sufficiently efficient hardware realization. The system’s numerical solution and hardware realization have two requirements. First, the delay terms are implemented by employing LookUp Tables to keep the already required delayed samples in the dynamical equations. Second, the fractional derivative is numerically approximated using Grünwald-Letnikov approximation with a memory window size, $L$ , according to the short memory principle such that it balances between accuracy and efficiency. Bifurcation diagrams and spectral entropy validate the chaotic behaviour of the system for commensurate and incommensurate orders. Additionally, the dynamic behaviour of the system is studied versus the delay parameter, $\tau $ , and the window size, $L$ . The system is realized on Nexys 4 Artix-7 FPGA XC7A100T with throughput 1.2 Gbit/s and hardware resources utilization 15% from the total LookUp Tables and 4% from the slice registers. Oscilloscope experimental results verify the numerical solution of the delayed fractional-order system. The amenability to digital hardware realization, which is experimentally validated in this article, is added to the system’s advantages and encourages its utilization in future digital applications such as chaos control and synchronization and chaos-based communication applications.

中文翻译：

---

分数阶时滞混沌系统的混沌动力学和FPGA实现

本文提出了一种数字解决方案方法和延迟分数阶系统的现场可编程门阵列实现。所提出的方法适合于足够有效的硬件实现。系统的数值解和硬件实现有两个要求。首先，通过使用查阅表来实现延迟项，以将已经需要的延迟样本保留在动力学方程式中。其次，分数阶导数是使用Grünwald-Letnikov逼近和内存窗口大小进行数值逼近的， $ L $ ，根据短存储原理，使其在准确性和效率之间取得平衡。分叉图和谱熵验证了系统在相称和不相称阶数时的混沌行为。此外，还针对延迟参数研究了系统的动态行为， $ \ tau $ ，以及窗口大小， $ L $ 。该系统在Nexys 4 Artix-7 FPGA XC7A100T上实现，吞吐量为1.2 Gbit / s，硬件资源利用率占Lookup表总数的15％，而分片寄存器占4％。示波器实验结果验证了延迟分数阶系统的数值解。本文通过实验验证了对数字硬件实现的适应性，这增加了系统的优势，并鼓励其在未来的数字应用程序中使用，例如混沌控制和同步以及基于混沌的通信应用程序。