A SPICE compatible compact modeling framework is discussed for Hot Carrier Degradation (HCD) stress spanning the entire drain ( $\text{V}_{\mathrm{ D}}$ ) and gate ( $\text{V}_{\mathrm{ G}}$ ) voltage space and wide range of temperature (T). It can model the HCD time kinetics measured using different methods such as shift in threshold voltage ( $\Delta {\mathrm{ V}}_{\mathrm{ T}}$ ), linear ( $\Delta {\mathrm{ I}}_{\mathrm{ DLIN}}$ ) and saturation ( $\Delta {\mathrm{ I}}_{\mathrm{ DSAT}}$ ) drain current and charge pumping current ( $\Delta {\mathrm{ I}}_{\mathrm{ CP}}$ ), for off and on-state stress. The model is validated using measured data from conventional, Lightly Doped Drain (LDD) and Drain Extended (DE) MOSFETs, FinFETs and Gate All Around Nano Sheet (GAA-NS) FETs. Parametric drift due to Bias Temperature Instability (BTI) stress in the presence of $\text{V}_{\mathrm{ D}}$ is included. Impact due to Self-Heating (SH) and BTI-HCD coupling are considered. SPICE compatibility is shown by cycle-by-cycle simulation of various Ring Oscillator (RO) circuits.

中文翻译：

---

全 VG-VD 空间、不同实验条件和不同设备架构下的 HCD 动力学建模

讨论了一个 SPICE 兼容的紧凑建模框架，用于跨越整个漏极的热载流子退化 (HCD) 应力（ $\text{V}_{\mathrm{ D}}$ ) 和门 ( $\text{V}_{\mathrm{ G}}$ ) 电压空间和较宽的温度范围 (T)。它可以模拟使用不同方法测量的 HCD 时间动力学，例如阈值电压的偏移（ $\Delta {\mathrm{ V}}_{\mathrm{ T}}$ ), 线性 ( $\Delta {\mathrm{ I}}_{\mathrm{ DLIN}}$ ) 和饱和度 ( $\Delta {\mathrm{ I}}_{\mathrm{ DSAT}}$ ) 漏极电流和电荷泵电流 ( $\Delta {\mathrm{ I}}_{\mathrm{ CP}}$ )，用于关断和通态应力。该模型使用来自传统、轻掺杂漏极 (LDD) 和漏极扩展 (DE) MOSFET、FinFET 和栅极环绕纳米片 (GAA-NS) FET 的测量数据进行验证。存在偏置温度不稳定性 (BTI) 应力引起的参数漂移 $\text{V}_{\mathrm{ D}}$ 已经包括了。考虑了由于自热 (SH) 和 BTI-HCD 耦合造成的影响。SPICE 兼容性通过各种环形振荡器 (RO) 电路的逐周期仿真来显示。