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Design of a Bit-Interleaved Low Power 10T SRAM Cell with Enhanced Stability
Journal of Circuits, Systems and Computers ( IF 1.5 ) Pub Date : 2020-12-10 , DOI: 10.1142/s0218126621501425
R. Manoj Kumar 1 , P. V. Sridevi 1
Affiliation  

The technology is shrinking in recent days which leads to growing concerns related to various design metrics. Leakage power tends to grow with the array size as most of the Static Random Access Memory (SRAM) cells operate in standby mode. The data to be written into the SRAM become difficult as the supply voltage decreases. So, stability in write mode requires enhancement. As SRAM is used for the on-chip computations, the faster write operation is required. The half-select issue in SRAM design needs to be eliminated so that bit interleaving architecture can be employed for the SRAM array enabling the protection from soft errors. A new Proposed 10 Transistor Bit-Interleaved SRAM cell has been designed addressing the above concerns. Employment of high-threshold voltage devices in read path and absence of NMOS device in one of the inverters reduces leakage power. Cut-off switch enables faster write operation and enhanced write stability. Cross point selection in write mode eliminates the half-select issue observed by carrying 1000 Monte-Carlo simulations. It has lower leakage power while holding 0 compared to 8 Transistor, Fully Differential 8 Transistor and Write Assist Low Power 11 Transistor SRAM cells at the worst fast-fast process corner for 0.9 V supply voltage. Write 1 Power Delay Product is lower than 8 Transistor, Fully Differential 8 Transistor and Write Assist Low Power 11 Transistor SRAM cells at slow-slow corner at 0.9V supply voltage. All the design metrics have been evaluated by performing post-layout simulation in Cadence Virtuoso in 45-nm technology.

中文翻译:

具有增强稳定性的位交错低功耗 10T SRAM 单元的设计

最近几天,该技术正在萎缩,这导致与各种设计指标相关的担忧日益增加。由于大多数静态随机存取存储器 (SRAM) 单元在待机模式下运行,因此泄漏功率往往会随着阵列大小而增长。随着电源电压的降低,要写入 SRAM 的数据变得困难。因此,写入模式的稳定性需要增强。由于 SRAM 用于片上计算,因此需要更快的写入操作。需要消除 SRAM 设计中的半选择问题,以便可以为 SRAM 阵列采用位交错架构,从而实现对软错误的保护。已经设计了一种新的提议的 10 晶体管位交错 SRAM 单元来解决上述问题。在读取路径中使用高阈值电压器件并且在其中一个反相器中不存在 NMOS 器件可降低泄漏功率。截止开关可实现更快的写入操作和增强的写入稳定性。写入模式下的交叉点选择消除了通过进行 1000 次蒙特卡罗模拟观察到的半选择问题。与 8 晶体管、全差分 8 晶体管和写入辅助低功耗 11 晶体管 SRAM 单元相比,它在保持 0 时具有更低的泄漏功率,在 0.9 V 电源电压下处于最差的快速工艺角。在 0.9V 电源电压下,写入 1 功率延迟乘积低于 8 晶体管、全差分 8 晶体管和写入辅助低功耗 11 晶体管 SRAM 单元。所有设计指标均已通过在 Cadence Virtuoso 中以 45 纳米技术执行布局后仿真进行评估。
更新日期:2020-12-10
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