The use of 3D-IC technology has become quite widespread in designing core-based systems-on-chip (SoCs). Concomitantly, testing of cores and inter-layer through-silicon-vias (TSVs) spanning through different layers of 3D chips has become an important problem in the manufacturing cycle. Testing 3D-SoCs is more challenging compared to their 2D counterparts because of the complexity of their design and power management issues. Also, the test procedure demands substantially more power than what is required in the normal functional mode, and hence, stringent thermal constraints during test need to be fulfilled to safeguard future performance and reliability of the chip. Since the overall 3D infrastructure depends on routing layer assignments, core allocation, and the geometry of TSV locations, these parameters should be given due consideration while designing the test-access-mechanism (TAM) that aims for minimizing overall test time satisfying power and TSV constraints. In this paper, we present a three-stage algorithm for reducing the test time in automated post-bond core-based 3D-SoCs, under a set of given constraints on test power, TAM-width, and the number of available TSVs. The proposed algorithm, when run on several ITC-02 SoC benchmarks, outperforms the algorithms presented in earlier work with respect to CPU-time, and additionally, reduces test time in many instances.

在设计基于内核的片上系统（SoC）时，3D-IC技术的使用已经非常普遍。随之而来的是，跨越3D芯片不同层的内核和层间硅直通孔（TSV）的测试已成为制造周期中的重要问题。与3D-SoC相比，由于其设计和电源管理问题的复杂性，测试3D-SoC更具挑战性。而且，测试过程所需的功率要比正常功能模式下所需的功率大得多，因此，在测试过程中必须满足严格的热约束条件，以保护芯片的未来性能和可靠性。由于整个3D基础架构取决于路由层分配，核心分配以及TSV位置的几何形状，在设计旨在最小化满足功率和TSV约束的总测试时间的测试访问机制（TAM）时，应适当考虑这些参数。在本文中，我们提出了一种三阶段算法，用于在基于测试功率，TAM宽度和可用TSV数量的一组给定约束下，减少基于自动键合后内核的3D-SoC的测试时间。当在多个ITC-02 SoC基准上运行时，提出的算法在CPU时间方面优于早期工作中提出的算法，此外，在许多情况下，它还减少了测试时间。在对测试功率，TAM宽度和可用TSV数量的一组给定约束下。当在多个ITC-02 SoC基准上运行时，提出的算法在CPU时间方面优于早期工作中提出的算法，此外，在许多情况下，它还减少了测试时间。在对测试功率，TAM宽度和可用TSV数量的一组给定约束下。当在多个ITC-02 SoC基准上运行时，提出的算法在CPU时间方面优于早期工作中提出的算法，此外，在许多情况下，它还减少了测试时间。