In this paper, a CMOS low noise amplifier (LNA) with very high linearization for ultra-wideband (UWB) applications is presented. In the proposed LNA, both second- and third-intercept points (IIP2 and IIP3) are improved by the new suggested post distortion star feedback (PDSF) technique in a wide frequency range. The star feedback circuit consists of three resistors that eliminate the nonlinear effect of the cascade transistor, and the PD circuit has an auxiliary transistor that eliminates the third-order non-linear coefficient of the main transistor. The post-layout simulation results of the proposed UWB LNA, which is designed using TSMC RF CMOS 65 ​nm, show the maximum power gain of 11 ​dB, minimum NF of 3.2 ​dB, and average IIP3 of 24 dBm in the frequency range of 3.1–10.6 ​GHz. In the designed circuit, the maximum IIP2 of 23.4 dBm is achieved. The chip area of the circuit is 0.874 ​mm², while the LNA consumes 15 ​mW from a 1.2 ​V supply voltage.

本文针对超宽带（UWB）应用，提出了一种具有很高线性度的CMOS低噪声放大器（LNA）。在建议的LNA中，通过新建议的后失真星形反馈（PDSF）技术在较宽的频率范围内，可以同时改善第二个和第三个拦截点（IIP2和IIP3）。星型反馈电路由三个电阻组成，这些电阻消除了级联晶体管的非线性影响，而PD电路具有一个辅助晶体管，该晶体管消除了主晶体管的三阶非线性系数。拟议的UWB LNA的布局后仿真结果是使用TSMC RF CMOS 65 nm设计的，显示在频率范围内的最大功率增益为11 dB，最小NF为3.2 dB，平均IIP3为24 dBm 3.1–10.6 GHz 在设计的电路中，最大IIP2为23.4 dBm。^{如图2所示}，而LNA从1.2伏电源电压消耗的功率为15毫瓦。