Microelectronics Journal ( IF 2.2 ) Pub Date : 2020-11-28 , DOI: 10.1016/j.mejo.2020.104938 Walter Schneider
The growing impact of process variations on circuit performance has become a major concern for deep-submicron integrated circuit design, resulting in numerous SSTA-algorithms. The acceptance of such algorithms in industry however will be dependent on modeling the real silicon behavior in SSTA. This includes that the statistical gate-delay models must consider arbitrary process variations and dependencies. In this paper, we introduce the innovative concept of Copulas to handle this topic. A complete Matlab based framework starting from process parameter statistics up to the computation of the statistical gate-delay distribution is presented. Experimental results demonstrate the importance of accounting realistic process variations.
中文翻译:
使用Copulas进行统计门延迟建模
工艺变化对电路性能的影响越来越大,已成为深亚微米集成电路设计的主要关注点,从而产生了许多SSTA算法。然而,这种算法在工业上的接受将取决于对SSTA中真实硅行为的建模。这包括统计门延迟模型必须考虑任意过程变化和依赖性。在本文中,我们介绍了Copulas的创新概念来处理此主题。提出了一个完整的基于Matlab的框架,从过程参数统计一直到统计门延迟分布的计算。实验结果证明了考虑实际过程变化的重要性。