Floorplanning problem has been extensively explored for homogeneous FPGAs. Most modern FPGAs consist of heterogeneous resources in the form of configurable logic blocks, DSP blocks, BRAMs and more. Very little work has been done for heterogeneous FPGAs. In addition, features like partial reconfigurability allow on-the-fly changes to the executable design that can result in enhanced performance and very efficient utilization of resources. In this paper, we have designed a floorplanner for Partially Reconfigurable (PR) designs in FPGA that smartly decides one of the three proposed resource allocation schemes to floorplan a particular type of reconfigurable region. We also propose a White Space Detection algorithm for efficient management of white space inside an FPGA in order to reduce the area and the wire length. The floorplanner is demonstrated on Xilinx Virtex 5 and Artix 7 FPGA architectures and can be easily integrated with existing vendor-supplied Place and Route tools. The main objective of the floorplanner is to reduce the wire length, minimize wasted resources and the area. The performance of our floorplanner is evaluated using MCNC benchmarks. We have compared our proposed floorplanner with other previously published results reported in the literature. We observe a substantial improvement in the overall wire length as well as the execution time. Also, the floorplanner was integrated with vendor supplied place and route tools (Xilinx Vivado) to automate the floorplanning flow. The automation process was tested on a partially reconfigurable median filter used in image processing applications.

中文翻译：

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异构FPGA上部分可重配置设计的自动布局规划

对于同类FPGA，已经广泛研究了布局规划问题。大多数现代FPGA均包含可配置逻辑块，DSP块，BRAM等形式的异构资源。异构FPGA所做的工作很少。另外，诸如部分可重新配置性之类的功能允许对可执行设计进行即时更改，从而可以提高性能并非常有效地利用资源。在本文中，我们为FPGA中的部分可重配置（PR）设计设计了一个平面规划器，该规划器巧妙地确定了三种建议的资源分配方案之一，以对特定类型的可重配置区域进行平面规划。我们还提出了一种白色空间检测算法，用于有效管理FPGA内部的白色空间，以减少面积和缩短导线长度。在Xilinx Virtex 5和Artix 7 FPGA架构上演示了布局规划器，并且可以轻松地将其与供应商提供的现有布局布线工具集成。平面布置图的主要目的是减少线长，最大程度地减少浪费的资源和面积。我们的平面布置图的性能是使用MCNC基准进行评估的。我们已经将我们建议的楼层平面图与文献中先前公布的其他结果进行了比较。我们观察到总体导线长度以及执行时间有了实质性的改善。此外，平面规划器还与供应商提供的布局和布线工具（Xilinx Vivado）集成在一起，可自动执行平面规划流程。自动化过程在用于图像处理应用程序的部分可重新配置的中值滤波器上进行了测试。