Signals in modern integrated circuits travel through complex interconnect structures, which present several layers and important coupling capacitance effects. Even more, the impact of signal coupling on the overall circuit behavior has grown with technology scaling as the interconnect have become taller. In this paper, a methodology to identify those logic paths more significantly influenced by the coupling capacitances is presented. The proposed methodology is based on a modified Dijkstra’s algorithm, which finds those paths between a primary input and a primary output more severely influenced by the coupling capacitances. This methodology can be used to validate circuit behavior and it can also be applied in testing techniques oriented to detect interconnect defects (e.g., opens and short defects). The proposed methodology is applied to ISCAS’85 benchmark circuits to show its feasibility.

中文翻译：

---

严重耦合电容影响的逻辑路径识别

现代集成电路中的信号通过复杂的互连结构传输，这些结构呈现出多层和重要的耦合电容效应。更重要的是，随着互连变得更高，信号耦合对整个电路行为的影响随着技术的扩展而增长。在本文中，提出了一种识别受耦合电容影响较大的逻辑路径的方法。所提出的方法基于改进的 Dijkstra 算法，该算法发现初级输入和初级输出之间的路径受耦合电容的影响更为严重。该方法可用于验证电路行为，也可应用于面向检测互连缺陷（例如，开路和短路缺陷）的测试技术。