In this paper, a rail-to-rail time-domain comparator with low power supply voltage and low power consumption is introduced. The comparator can be employed in low-power converters and biomedical applications. In the proposed time-domain comparator, a rail-to-rail delay element has been employed to generate a significant voltage-to-time gain for the full range of input signals. This circuit is designed, laid out, and simulated in 0.18 μm TSMC technology and powered by 0.6 V and 1 V supply voltages. The simulation results show that the proposed comparator has a rail-to-rail dynamic range and the power consumption of the circuit is 0.6 μW and 19 μW at the clock frequency of 10 MHz and 100 MHz, respectively. The active area of 56 μm × 14 μm shows the compactness of the circuit comparing to the other similar works. The proposed comparator was used in an ADC to show its effectiveness to improve the performance of the ADC. An 8-bit 0.8 V 100 kS/s SAR-ADC is designed and simulated. It consumes 430 nW and the figure of merit is 19.3fJ/conversion-step.

本文介绍了一种具有低电源电压和低功耗的轨到轨时域比较器。该比较器可用于低功率转换器和生物医学应用。在提出的时域比较器中，采用了轨到轨延迟元件来为整个输入信号范围产生明显的电压到时间增益。该电路采用0.18μmTSMC技术进行设计，布局和仿真，并由0.6 V和1 V电源电压供电。仿真结果表明，所提出的比较器具有轨到轨的动态范围，并且在10 MHz和100 MHz的时钟频率下电路的功耗分别为0.6μW和19μW。与其他类似作品相比，56μm×14μm的有效面积显示了电路的紧凑性。拟议的比较器用于ADC中，以显示其改善ADC性能的有效性。设计并仿真了8位0.8 V 100 kS / s SAR-ADC。它的功耗为430 nW，品质因数为19.3fJ /转换步长。