In this paper, we provide a new procedure that allows to design a generic three-stage amplifier from settling-time specifications. The procedure analyze the settling-time of pure two- or three-pole amplifiers (i.e., with no zeros) and extends the results to a generic amplifier that includes one or two zeros even placed in the right-half plane. The validity of the proposed approach is demonstrated through a design example of a three-stage CMOS amplifier suitable for switched-capacitor applications.

中文翻译：

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接近最小稳定时间的CMOS三级放大器设计

在本文中，我们提供了一种新的程序，该程序允许根据建立时间规格设计通用的三级放大器。该过程分析了纯两极或三极放大器（即没有零）的建立时间，并将结果扩展到包括一个或两个甚至位于右半平面的零的通用放大器。通过适用于开关电容器应用的三级CMOS放大器的设计实例证明了该方法的有效性。