The complexity of intra prediction in High-Efficiency Video Coding (HEVC) is increased significantly due to the incorporation of inherent features like variable-sized quadtree partitioned coding units and 35 angular modes that help in achieving better compression. This paper presents an efficient hardware architecture for the intra prediction that supports and comprises the above aspects and achieves a higher throughput to support high definition (HD) videos. A compact reusable reference buffer structure is implemented to limit the buffer size to 1 KB. A dedicated arithmetic unit to take advantage of the parallelism present in the prediction algorithm is incorporated, which allows the reuse of multipliers to reduce hardware resources. The loading of reference samples to buffers for prediction causes significant delays which are eliminated in our design. The entire architecture functions as a pipelined unit with no data dependency and generates eight samples/clock cycle in parallel. The design is implemented on a Field Programmable Gate Array (FPGA) platform operating at a frequency of 110 MHz. This makes it possible to support 4 K videos at 30 frames per second, with the resource cost of 16 K logic gates and 122 registers.

高效视频编码 (HEVC) 中帧内预测的复杂性显着增加，这是由于结合了可变大小的四叉树分区编码单元和 35 种角度模式等固有特征，有助于实现更好的压缩。本文提出了一种有效的帧内预测硬件架构，该架构支持并包含上述方面，并实现了更高的吞吐量以支持高清 (HD) 视频。实现了一个紧凑的可重用参考缓冲区结构，以将缓冲区大小限制为 1 KB。并入了一个利用预测算法中存在的并行性的专用算术单元，它允许重用乘法器以减少硬件资源。将参考样本加载到缓冲区进行预测会导致明显的延迟，这在我们的设计中被消除了。整个架构作为一个流水线单元运行，没有数据依赖性，并行生成 8 个样本/时钟周期。该设计在以 110 MHz 频率运行的现场可编程门阵列 (FPGA) 平台上实现。这使得以每秒 30 帧的速度支持 4K 视频成为可能，而资源成本为 16K 逻辑门和 122 个寄存器。