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Improving SSD Read Latency via Coding
IEEE Transactions on Computers ( IF 3.7 ) Pub Date : 2020-12-01 , DOI: 10.1109/tc.2020.2978823
Hyegyeong Park , Jaekyun Moon

We study the potential enhancement of the read access speed in high-performance solid-state drives (SSDs) by coding, given speed variations across the multiple flash interfaces and assuming occasional local memory failures. Our analysis is based on a queuing model that incorporates both read request failures and NAND element failures. The NAND element failure in the present context reflects various limitations on the memory element level such as bad blocks, dies or chips that cannot be corrected by error control coding (ECC) typically employed to protect pages read off the NAND cells. Our analysis provides a clear picture of the storage-overhead and read-latency trade-offs given read failures and NAND element failures. We investigate two different ways to mitigate the effect of NAND element failures using the notion of multi-class jobs with different priorities. A strong motivation for this work is to understand the reliability requirement of NAND chip components given an additional layer of failure protection, under the latency/storage-overhead constraints.

中文翻译:

通过编码改善 SSD 读取延迟

我们通过编码研究了高性能固态驱动器 (SSD) 中读取访问速度的潜在增强,考虑到多个闪存接口的速度变化并假设偶尔出现本地内存故障。我们的分析基于一个队列模型,该模型包含读取请求失败和 NAND 元素失败。当前上下文中的 NAND 元件故障反映了存储元件级别的各种限制,例如无法通过错误控制编码 (ECC) 纠正的坏块、管芯或芯片,通常用于保护从 NAND 单元读取的页面。我们的分析清楚地说明了考虑到读取失败和 NAND 元件失败的存储开销和读取延迟的权衡。我们使用具有不同优先级的多类作业的概念研究了两种不同的方法来减轻 NAND 元件故障的影响。这项工作的一个强烈动机是了解 NAND 芯片组件在延迟/存储开销限制下给定额外的故障保护层的可靠性要求。
更新日期:2020-12-01
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