This paper proposes a technique that uses the number of oscillation cycles (NOC) of a VCO-based comparator to set multiple adaptive bypass windows in a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). The analysis of the number of bit cycles, power and static performance shows that three adaptive bypass windows reduce power consumption, and decrease DNL and have similar INL, compared with the SAR ADC without bypass windows. In addition, a 1-bit split-and-recombination redundancy technique and a general bypass logic digital error correction method are proposed to address the settling issues and optimize the size of the bypass window. This design is implemented in 40 nm CMOS technology. The conversion frequency of the ADC reaches up to 30 MS/s. The ADC achieves an SFDR of 85.35 dB and 11.12-bit ENOB with Nyquist input, consuming 380 μW, down from 427 μW without multiple adaptive bypass windows, at a 1.1 V supply, resulting in a figure of merit (FoM) of 5.69 fJ/conversion-step.

中文翻译：

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具有 NOC 辅助的多个自适应旁路窗口的 12 位 30-MS/s 基于 VCO 的 SAR ADC

本文提出了一种技术，该技术使用基于 VCO 的比较器的振荡周期 (NOC) 数在 12 位逐次逼近寄存器 (SAR) 模数转换器 (ADC) 中设置多个自适应旁路窗口。对位周期数、功耗和静态性能的分析表明，与没有旁路窗口的SAR ADC相比，三个自适应旁路窗口降低了功耗，降低了DNL并具有相似的INL。此外，还提出了 1 位拆分和重组冗余技术和通用旁路逻辑数字纠错方法，以解决建立问题并优化旁路窗口的大小。此设计采用 40 纳米 CMOS 技术实现。ADC 的转换频率高达 30 MS/s。ADC 实现了 85.35 dB 和 11 的 SFDR。