The successive approximation register (SAR) is one of the most energy-efficient analog-to-digital converter (ADC) architecture for medium-resolution applications. However, its high energy efficiency quickly diminishes when the target resolution increases. This is because a SAR ADC suffers from several major error source, including the sampling kT/C noise, the comparator noise, and the DAC mismatch. These errors are increasing hard to address in high-resolution SAR ADCs. This paper reviews recent advances on error suppression techniques for SAR ADCs, including the sampling kT/C noise reduction, the noise-shaping (NS) SAR, and the mismatch error shaping (MES). These techniques aim to boost the resolution of SAR ADCs while maintaining their superior energy efficiency.

中文翻译：

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用于高能效高分辨率 SAR ADC 的误差抑制技术

逐次逼近寄存器 (SAR) 是适用于中等分辨率应用的最节能的模数转换器 (ADC) 架构之一。然而，当目标分辨率增加时，其高能效会迅速降低。这是因为 SAR ADC 受到几个主要误差源的影响，包括采样 kT/C 噪声、比较器噪声和 DAC 失配。这些错误越来越难以在高分辨率 SAR ADC 中解决。本文回顾了 SAR ADC 误差抑制技术的最新进展，包括采样 kT/C 降噪、噪声整形 (NS) SAR 和失配误差整形 (MES)。这些技术旨在提高 SAR ADC 的分辨率，同时保持其卓越的能效。