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3D TCAD Analysis Enabling ESD Layout Design Optimization
IEEE Journal of the Electron Devices Society ( IF 2.3 ) Pub Date : 2020-01-01 , DOI: 10.1109/jeds.2020.3027034
Zijin Pan , Cheng Li , Mengfu Di , Feilong Zhang , Albert Wang

On-chip electrostatic discharge (ESD) protection design for integrated circuits (ICs) is a challenging design-for-reliability problem. Since ESD events involve very high current transients in very short time period, current crowding is unavoidable, which leads to local overheating and creates local hot spots, resulting in ESD thermal failures. Therefore, layout design plays a critical role in practical ESD protection designs, which cannot be addressed by 2D TCAD ESD simulation. This article reports a comprehensive ESD simulation analysis by comparing true 3D TCAD with 2D TCAD, using exemplar diode ESD devices in a 55nm CMOS, which reveals 3D ESD discharging behaviors upon ESD layout variations. It concludes that true 3D TCAD ESD simulation is a powerful technique to enable ESD layout design optimization in real-world ESD protection designs.

中文翻译:

支持 ESD 版图设计优化的 3D TCAD 分析

集成电路 (IC) 的片上静电放电 (ESD) 保护设计是一个具有挑战性的可靠性设计问题。由于 ESD 事件在很短的时间内涉及非常大的电流瞬变,因此电流拥挤是不可避免的,这会导致局部过热并产生局部热点,从而导致 ESD 热失效。因此,版图设计在实际 ESD 保护设计中起着至关重要的作用,这是 2D TCAD ESD 仿真无法解决的问题。本文通过比较真正的 3D TCAD 和 2D TCAD,使用 55 纳米 CMOS 中的示例二极管 ESD 器件报告了全面的 ESD 模拟分析,揭示了 ESD 布局变化时的 3D ESD 放电行为。它得出的结论是,真正的 3D TCAD ESD 仿真是一种强大的技术,可以在实际 ESD 保护设计中实现 ESD 布局设计优化。
更新日期:2020-01-01
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