This study introduces the design of true random number generator (TRNG) using jitter, metastability and current starved topology. The proposed design consisted of a current starved inverter-based ring oscillator (RO) with a high-frequency divider block (designed by T-FF followed by D-FF to address setup and hold time issues), jitter extraction and metastable block followed by two sampling blocks. The design avails fewer amenities to yield the reduction in hardware and enhances the degree of randomness. The post-layout simulation of the proposed work was performed using a 180 nm CMOS technology environment in the Cadence Virtuoso tool. The speed and power dissipation achieved are 1.5 Gbps and 0.4 mW, respectively, with an efficiency of 0.27 pJ/bit. The effect of temperature and variation in supply voltages (by 10% around its nominal value) is also investigated on the generated random numbers through parametric analysis. For validation of randomness, the generated random signals are first sampled and then converted in binary format using MATLAB and finally verified by Kolmogorov–Smirnov and Chi-square test for the uniformity and independency. The validity of the proposed work is done by NIST 800.22 statistical test suite. The proposed TRNG design achieved a very high-pass efficiency.

中文翻译：

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具有抖动，亚稳定性和电流不足拓扑的0.4 mW，0.27 pJ / bit真随机数发生器

本研究介绍了利用抖动，亚稳定性和电流不足的拓扑结构设计的真随机数发生器（TRNG）。拟议的设计包括一个电流不足的基于逆变器的环形振荡器（RO）和一个高频分频器模块（由T-FF设计，然后由D-FF设计，以解决建立和保持时间问题），抖动提取和亚稳模块，其次是两个采样块。该设计利用较少的便利设施来减少硬件并提高随机性。在Cadence Virtuoso工具中使用180 nm CMOS技术环境对拟议工作进行了布局后仿真。实现的速度和功耗分别为1.5 Gbps和0.4 mW，效率为0.27 pJ / bit。通过参数分析，还研究了温度和电源电压变化（在其标称值附近降低10％）的影响，对生成的随机数进行了研究。为了验证随机性，首先对生成的随机信号进行采样，然后使用MATLAB将其转换为二进制格式，最后通过Kolmogorov–Smirnov和卡方检验验证其均匀性和独立性。提议的工作的有效性由NIST 800.22统计测试套件完成。提出的TRNG设计实现了非常高的通过效率。提议的工作的有效性由NIST 800.22统计测试套件完成。提出的TRNG设计实现了非常高的通过效率。提议的工作的有效性由NIST 800.22统计测试套件完成。提出的TRNG设计实现了非常高的通过效率。