A novel multi-stage pipelined extended-counting (EC) for 3D-stacked CMOS image sensors is presented, which combines the benefits of a pipelined ADC, a first-order ADC and the EC principle in order to simultaneously achieve a high resolution and a high frame rate for 3D-stacked imagers. By assigning each stage of the pipeline to a sub-column of pixels while choosing another input stage of the pipeline when a sub-column has been read out, discontinuous rolling shutter artefacts like chopped images can be eliminated and frame rates up to 340 fps can be achieved for imagers with 8 K resolution.

中文翻译：

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流水线扩展计数 $ {\ bf I \ Delta \ Sigma} $一世ΔΣ 用于3D堆叠CMOS图像传感器

一种新颖的多阶段流水线扩展计数（EC） 提出了一种用于3D堆叠CMOS图像传感器的产品，该产品结合了流水线ADC的优势，即一阶 ADC和EC原理，以便同时为3D堆叠成像器实现高分辨率和高帧率。通过在将子列读出后，将流水线的每一级分配给一个像素子列，同时选择流水线的另一个输入级，可以消除不连续的滚动快门伪像（例如切碎的图像），并且可以达到340 fps的帧速率分辨率为8 K的成像仪可以实现。