This Letter proposes a single event double-upset (SEDU)-fully-tolerant latch, referred to as FBSET, mainly featuring four interlocked branch circuits implemented by stacking three PMOS and one NMOS transistors or three NMOS and one PMOS transistors to achieve low power dissipation. The latch exhibits up to 84.56% area-power-delay product saving compared with recently reported latches. Simulation results validate that the proposed latch is completely immune to SEDU.

中文翻译：

---

高性能单事件双加扰免疫锁存器设计

本文提出了一种单事件双加扰 (SEDU) 完全容错锁存器，简称 FBSET，主要具有四个互锁分支电路，通过堆叠三个 PMOS 和一个 NMOS 晶体管或三个 NMOS 和一个 PMOS 晶体管来实现低功耗. 与最近报道的锁存器相比，该锁存器可节省高达 84.56% 的面积功率延迟积。仿真结果验证了所提出的锁存器完全不受 SEDU 影响。