Data processing systems based on FPGAs offer high performance and energy efficiency for a variety of applications. However, these advantages are achieved through highly specialized designs. The high degree of specialization leads to accelerators with narrow functionality and designs adhering to a rigid execution flow. For multi-tenant systems this limits the scope of applicability of FPGA-based accelerators, because, first, supporting a single operation is unlikely to have any significant impact on the overall performance of the system, and, second, serving multiple users satisfactorily is difficult due to simplistic scheduling policies enforced when using the accelerator. Standard operating system and database management system features that would help address these limitations, such as context-switching, preemptive scheduling, and thread migration are practically non-existent in current FPGA accelerator efforts. In this work, we propose PipeArch, an open-source project 1 for developing FPGA-based accelerators that combine the high efficiency of specialized hardware designs with the generality and functionality known from conventional CPU threads. PipeArch provides programmability and extensibility in the accelerator without losing the advantages of SIMD-parallelism and deep pipelining. PipeArch supports context-switching and thread migration, thereby enabling for the first time new capabilities such as preemptive scheduling in FPGA accelerators within a high-performance data processing setting. We have used PipeArch to implement a variety of machine learning methods for generalized linear model training and recommender systems showing empirically their advantages over a high-end CPU and even over fully specialized FPGA designs.

中文翻译：

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管拱

基于 FPGA 的数据处理系统为各种应用提供高性能和高能效。然而，这些优势是通过高度专业化的设计来实现的。高度专业化导致加速器功能狭窄，设计遵循严格的执行流程。对于多租户系统，这限制了基于 FPGA 的加速器的适用范围，因为，首先，支持单个操作不太可能对系统的整体性能产生任何重大影响，其次，很难令人满意地为多个用户提供服务由于使用加速器时强制执行的简单调度策略。有助于解决这些限制的标准操作系统和数据库管理系统功能，例如上下文切换、抢占式调度、在当前的 FPGA 加速器工作中几乎不存在线程迁移。在这项工作中，我们提出了 PipeArch，一个开源项目1用于开发基于 FPGA 的加速器，将专用硬件设计的高效率与传统 CPU 线程已知的通用性和功能相结合。PipeArch 在加速器中提供了可编程性和可扩展性，同时又不失 SIMD 并行性和深度流水线的优势。PipeArch 支持上下文切换和线程迁移，从而在高性能数据处理设置中首次启用新功能，例如 FPGA 加速器中的抢占式调度。我们已经使用 PipeArch 为广义线性模型训练和推荐系统实现了各种机器学习方法，凭经验展示了它们相对于高端 CPU 甚至完全专业化 FPGA 设计的优势。