The ever-increasing quest for data-level parallelism and variable precision in ubiquitous multimedia and Deep Neural Network (DNN) applications has motivated the use of Single Instruction, Multiple Data (SIMD) architectures. To alleviate energy as their main resource constraint, approximate computing has re-emerged,albeit mainly specialized for their Application-Specific Integrated Circuit (ASIC) implementations. This paper, presents for the first time, an SIMD architecture based on novel multiplier and divider with tunable accuracy, targeted for Field-Programmable Gate Arrays (FPGAs). The proposed hybrid architecture implements Mitchell's algorithms and supports precision variability from 8 to 32 bits. Experimental results obtained from Vivado, multimedia and DNN applications indicate superiority of proposed architecture (both SISD and SIMD) over accurate and state-of-the-art approximate counterparts. In particular, the proposed SISD divider outperforms the accurate Intellectual Property (IP) divider provided by Xilinx with 4x higher speed and 4.6x less energy and tolerating only < 0.8% error. Moreover, the proposed SIMD multiplier-divider supersede accurate SIMD multiplier by achieving up to 26%, 45%, 36%, and 56% improvement in area, throughput, power, and energy, respectively.

中文翻译：

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SIMDive：用于具有可调精度的 FPGA 的近似 SIMD 软乘法器-除法器

在无处不在的多媒体和深度神经网络 (DNN) 应用程序中，对数据级并行性和可变精度的不断追求促使了单指令多数据 (SIMD) 架构的使用。为了缓解作为其主要资源约束的能源，近似计算重新出现，尽管主要专门用于其专用集成电路 (ASIC) 实现。本文首次介绍了一种基于新型乘法器和除法器的 SIMD 架构，具有可调精度，适用于现场可编程门阵列 (FPGA)。所提出的混合架构实现了 Mitchell 的算法并支持从 8 位到 32 位的精度可变性。从 Vivado 获得的实验结果，多媒体和 DNN 应用表明所提出的架构（SISD 和 SIMD）优于准确和最先进的近似对应物。特别是，所提议的 SISD 分频器优于 Xilinx 提供的精确知识产权 (IP) 分频器，速度提高了 4 倍，能量降低了 4.6 倍，并且仅允许 < 0.8% 的误差。此外，所提出的 SIMD 乘法器-除法器在面积、吞吐量、功率和能量方面分别实现了高达 26%、45%、36% 和 56% 的改进，从而取代了精确的 SIMD 乘法器。