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Mitigating Write Disturbance Errors of Phase-Change Memory as In-Module Approach
arXiv - CS - Hardware Architecture Pub Date : 2020-11-01 , DOI: arxiv-2011.00448
Hyokeun Lee, Seungyong Lee, Byeongki Song, Moonsoo Kim, Seokbo Shim, Hyun Kim, Hyuk-Jae Lee

With the growing demand for technology scaling and storage capacity in server systems to support high-performance computing, phase-change memory (PCM) has garnered attention as the next-generation non-volatile memory to satisfy these requirements. However, write disturbance error (WDE) appears as a serious reliability problem preventing PCM from general commercialization. WDE occurs on the neighboring cells of a written cell due to heat dissipation. Previous studies for the prevention of WDEs are based on the write cache or verify-n-correction while they often suffer from significant area overhead and performance degradation, making it unsuitable for high-performance computing. Therefore, an on-demand correction is required to minimize the performance overhead. In this paper, an in-module disturbance barrier (IMDB) mitigating WDEs is proposed. IMDB includes two sets of SRAMs into two levels and evicts entries with a policy that leverages the characteristics of WDE. In this work, the comparator dedicated to the replacement policy requires significant hardware resources and latency. Thus, an approximate comparator is designed to reduce the area and latency considerably. Furthermore, the exploration of architecture parameters is conducted to obtain cost-effective design. The proposed work significantly reduces WDEs without a noticeable speed degradation and additional energy consumption compared to previous methods.

中文翻译:

作为模块内方法减轻相变存储器的写干扰错误

随着服务器系统对支持高性能计算的技术扩展和存储容量的需求不断增长,相变存储器 (PCM) 作为满足这些要求的下一代非易失性存储器而受到关注。然而,写干扰错误 (WDE) 作为严重的可靠性问题出现,阻碍了 PCM 的普遍商业化。由于散热,WDE 发生在写入单元的相邻单元上。以前预防 WDE 的研究是基于写缓存或验证 n 校正,而它们经常遭受显着的面积开销和性能下降,使其不适用于高性能计算。因此,需要进行按需校正以最小化性能开销。在本文中,提出了一种减轻 WDE 的模块内干扰屏障 (IMDB)。IMDB 将两组 SRAM 分为两个级别,并使用利用 WDE 特性的策略驱逐条目。在这项工作中,专用于替换策略的比较器需要大量的硬件资源和延迟。因此,设计了近似比较器以显着减少面积和延迟。此外,还对架构参数进行了探索,以获得具有成本效益的设计。与以前的方法相比,拟议的工作显着减少了 WDE,而没有明显的速度下降和额外的能源消耗。近似比较器旨在显着减少面积和延迟。此外,还对架构参数进行了探索,以获得具有成本效益的设计。与以前的方法相比,拟议的工作显着减少了 WDE,而没有明显的速度下降和额外的能源消耗。近似比较器旨在显着减少面积和延迟。此外,还对架构参数进行了探索,以获得具有成本效益的设计。与以前的方法相比,拟议的工作显着减少了 WDE,而没有明显的速度下降和额外的能源消耗。
更新日期:2020-11-06
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