Abstract

In this work, drain current I_D for 7-nm gate length dual-material (DM) cylindrical gate all around (CGAA) silicon nanowire (SiNW) has been studied and simulation results are reported using Silvaco ATLAS 3D TCAD. In this device, we consider the non-equilibrium Green’s function (NEGF) approach and self-consistent solution of Schrödinger's equation with Poisson’s equation. The splitting of conduction in multiple sub-bands has been considered and there is no doping in the channel region. The effect of DM gate engineering (variation of screen gate and control gate length having different work function) for SiNW channel with 2-nm radius and gate oxide (SiO₂) thickness of 0.8 nm on I_D have been studied. It was found that DM gate engineering reduces drain-induced barrier lowering (DIBL) but it also slightly increases sub-threshold slope (SS). This work has obtained small DIBL (~54 mV/V), small SS (~68 mV/dec), and higher I_On/I_Off (~4 × 10⁸) ratio as compared to literature concerning the inversion mode devices. The smallest DIBL is obtained when control gate length is the highest, and vice versa. With increase in control gate length, there is also increase in both I_On and I_Off but I_On/I_Off ratio decreases.

中文翻译：

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双材料栅极工程技术可减少围绕Si纳米线MOSFET的圆柱形栅极的DIBL，栅极长度为7 nm

摘要

在这项工作中，已经_研究了7纳米栅极长度双材料（DMAA）圆柱形整体栅极（CGAA）硅纳米线（SiNW）的漏极电流I _D，并使用Silvaco ATLAS 3D TCAD报告了仿真结果。在该设备中，我们考虑了非平衡格林函数（NEGF）方法以及Schrödinger方程与Poisson方程的自洽解。已经考虑了多个子带中的传导分裂，并且在沟道区域中没有掺杂。DM栅工程为硅纳米线信道（屏栅极和控制栅极长度具有不同功函数的变化）与2-纳米半径和栅极氧化物的效果（SIO ₂）上的0.8纳米厚我_d已经研究过了。已发现DM栅极工程可减少漏极引起的势垒降低（DIBL），但也会略微增加亚阈值斜率（SS）。与关于反转模式器件的文献相比，这项工作获得了较小的DIBL（〜54 mV / V），较小的SS（〜68 mV / dec）和更高的I _On / I _Off（〜4 ×10 ⁸）比。当控制栅极长度最大时，将获得最小的DIBL，反之亦然。随着控制栅极长度的增加，I _On和I _Off也会增加，但是I _On / I _Off比率会降低。