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Design of Low Power with Expanded Noise Margin Subthreshold 12T SRAM Cell for Ultra-Low Power Devices
Journal of Circuits, Systems and Computers ( IF 1.5 ) Pub Date : 2020-10-27 , DOI: 10.1142/s0218126621501061
Harekrishna Kumar 1 , V. K. Tomar 1
Affiliation  

In the proposed work, a differential write and single-ended read half-select free 12 transistors static random access memory cell is designed and simulated. The proposed cell has a considerable reduction in power dissipation with better stability and moderate performance. This cell operates in subthreshold region and has a higher value of read static noise margin as compared to conventional six transistors static random access memory cell. A power cut-off technique is utilized between access and pull-up transistors during the write operation. It results in an increase in write static noise margin as compared to all considered cells. In the proposed cell, read and write access time is improved along with a reduction in read/write power dissipation as compared to conventional six transistors static random access memory cell. The bitline leakage current in the proposed cell is reduced which improves the Ion/Ioff ratio of the cell under subthreshold region. The proposed cell occupies less area as compared to considered radiation-hardened design 12 transistors static random access memory cell. The computed electrical quality metric of proposed cell is better among considered static random access memory cells. Process variation analysis of read stability, access time, power dissipation, read current and leakage current has been performed with the help of Monte Carlo simulation at 3,000 points to get more soundness in the results. All characteristics of static random access memory cells are compared at various supply voltages.

中文翻译:

用于超低功耗器件的具有扩展噪声容限亚阈值 12T SRAM 单元的低功耗设计

在所提出的工作中,设计和仿真了一个差分写入和单端读取半选择自由 12 晶体管静态随机存取存储器单元。所提出的电池具有更好的稳定性和中等性能的功耗显着降低。与传统的六晶体管静态随机存取存储器单元相比,该单元在亚阈值区域中运行并且具有更高的读取静态噪声容限值。在写入操作期间,在存取晶体管和上拉晶体管之间使用了断电技术。与所有考虑的单元相比,它导致写入静态噪声容限增加。在所提出的单元中,与传统的六晶体管静态随机存取存储器单元相比,读取和写入存取时间随着读取/写入功耗的降低而得到改善。一世/一世离开阈下区域细胞的比率。与所考虑的抗辐射设计 12 晶体管静态随机存取存储器单元相比,所提出的单元占用的面积更小。在所考虑的静态随机存取存储器单元中,所提议单元的计算电气质量度量更好。借助蒙特卡罗模拟在 3,000 点进行了读取稳定性、访问时间、功耗、读取电流和泄漏电流的过程变化分析,以获得更可靠的结果。在各种电源电压下比较静态随机存取存储器单元的所有特性。
更新日期:2020-10-27
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