The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing in-memory computing (IMC) solutions to the fore. Since large data sets are usually stored in nonvolatile memory (NVM), various solutions have been proposed based on emerging memories, such as OxRAM, that rely mainly on area hungry, one transistor (1T) one OxRAM (1R) bit-cell. To tackle this area issue, while keeping the programming control provided by 1T1R bit-cell, we propose to combine gate-all-around stacked junctionless nanowires (1JL) and OxRAM (1R) technology to create a 3-D memory pillar with ultrahigh density. Nanowire junctionless transistors have been fabricated, characterized, and simulated to define current conditions for the whole pillar. Finally, based on Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, we demonstrated successfully scouting logic operations up to three-pillar layers, with one operand per layer.

中文翻译：

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用于内存计算应用的具有堆叠无结纳米线的超高密度 3-D 垂直 RRAM

冯诺依曼瓶颈是数据密集型应用程序的明显限制，使内存计算 (IMC) 解决方案脱颖而出。由于大数据集通常存储在非易失性存储器 (NVM) 中，因此已经提出了基于新兴存储器（例如 OxRAM）的各种解决方案，这些存储器主要依赖于占用面积、一个晶体管 (1T) 和一个 OxRAM (1R) 位单元。为了解决这个面积问题，在保持 1T1R 位单元提供的编程控制的同时，我们建议结合全栅堆叠无结纳米线 (1JL) 和 OxRAM (1R) 技术来创建具有超高密度的 3-D 存储器支柱. 纳米线无结晶体管已被制造、表征和模拟，以定义整个支柱的电流条件。最后，基于具有集成电路重点的仿真程序 (SPICE) 仿真，