Nowadays, hyperspectral imaging is recognized as a cornerstone remote sensing technology. Next generation, high-speed airborne, and space-borne imagers have increased resolution, resulting in an explosive growth in data volume and instrument data rate in the range of gigapixel per second. This competes with limited on-board resources and bandwidth, making hyperspectral image compression a mission critical on-board processing task. At the same time, the “new space” trend is emerging, where launch costs decrease, and agile approaches are exploited building smallsats using commercial-off-the-shelf (COTS) parts. In this contribution, we introduce a high-performance parallel implementation of the CCSDS-123.0-B-1 hyperspectral compression algorithm targeting SRAM field-programmable gate array (FPGA) technology. The architecture exploits image segmentation to provide the robustness to data corruption and enables scalable throughput performance by leveraging segment-level parallelism. Furthermore, we exploit the capabilities of a COTS FPGA system-on-chip (SoC) device to optimize size, weight, power, and cost (SWaP-C). The architecture partitions a hyperspectral cube stored in a DRAM framebuffer into segments, compressing them in parallel using a flexible software scheduler hosted in the SoC CPU and several compressor accelerator cores in the FPGA fabric. A 5-core implementation demonstrated on a Zynq-7045 FPGA achieves a throughput performance of 1387 Msamples/s [22.2 Gb/s at 16 bits per pixel per band (bpppb)] and outperforms previous implementations in equivalent FPGA technology, allowing seamless integration with next-generation hyperspectral sensors.

中文翻译：

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用于并行高光谱图像压缩的高性能 COTS FPGA SoC，采用 CCSDS-123.0-B-1

目前，高光谱成像已被公认为遥感技术的基石。下一代高速机载和星载成像仪的分辨率提高，导致数据量和仪器数据速率在每秒千兆像素范围内爆炸式增长。这与有限的机载资源和带宽竞争，使高光谱图像压缩成为一项关键任务机载处理任务。与此同时，“新空间”趋势正在出现，发射成本降低，使用商业现货（COTS）部件构建小卫星的敏捷方法被开发利用。在这篇文章中，我们介绍了针对 SRAM 现场可编程门阵列 (FPGA) 技术的 CCSDS-123.0-B-1 高光谱压缩算法的高性能并行实现。该架构利用图像分割来提供对数据损坏的鲁棒性，并通过利用段级并行性实现可扩展的吞吐量性能。此外，我们利用 COTS FPGA 片上系统 (SoC) 设备的功能来优化尺寸、重量、功耗和成本 (SWaP-C)。该架构将存储在 DRAM 帧缓冲区中的高光谱立方体划分为多个段，并使用 SoC CPU 中托管的灵活软件调度程序和 FPGA 架构中的多个压缩器加速器内核并行压缩它们。在 Zynq-7045 FPGA 上演示的 5 核实现实现了 1387 Msamples/s [22.2 Gb/s at 16 bits per band (bpppb)] 并优于先前在等效 FPGA 技术中的实现，允许与下一代高光谱传感器。