Aiming at reducing the complexity of minimum mean square error (MMSE) detection in massive multiple-input multiple-output (MIMO) systems, this paper proposes a detection algorithm with high convergence rate and an efficient hardware architecture based on second-order Richardson iteration (SORI). In the proposed algorithm, a pre-iteration-based initialization method is presented to accelerate the convergence without extra complexity. In addition, the approximation of relaxation factor and the log-likelihood ratio (LLR) is introduced to further reduce computing load. Theoretical analysis demonstrates the advantages of the proposed algorithm in fast convergence and low complexity, and simulation results show that the proposed algorithm can efficiently approach MMSE performance. Based on this algorithm, a flexible hardware architecture is designed, which is deeply pipelined to support $128\times U$ ( $8\leq U\leq 32$ ) massive MIMO detection with the configurable number of iterations, and a folded dual-mode systolic array (DMSA) is fully utilized to achieve the flexibility with low hardware consumption. Implemented on Xilinx Virtex-7 FPGA and SMIC 40nm CMOS technology, the proposed detector is competitive in terms of energy and area efficiency compared to state-of-the-art iterative detectors, and it can adapt to the varied channel condition and the number of users in massive MIMO systems.

中文翻译：

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基于二阶理查森迭代的高效大规模 MIMO 检测器：从算法到灵活架构

针对降低大规模多输入多输出(MIMO)系统中最小均方误差(MMSE)检测的复杂度，提出一种基于二阶Richardson迭代的具有高收敛速度和高效硬件架构的检测算法。索里）。在所提出的算法中，提出了一种基于预迭代的初始化方法来加速收敛而不增加额外的复杂性。此外，还引入了松弛因子和对数似然比 (LLR) 的近似值，以进一步降低计算负载。理论分析证明了该算法收敛速度快、复杂度低的优点，仿真结果表明该算法能有效逼近MMSE性能。基于该算法，设计了灵活的硬件架构，深度流水线支持 $128\times U$ ( $8\leq U\leq 32$ ) 具有可配置迭代次数的大规模 MIMO 检测，并充分利用折叠双模脉动阵列 (DMSA) 实现灵活性硬件消耗低。在 Xilinx Virtex-7 FPGA 和 SMIC 40nm CMOS 技术上实现，与最先进的迭代检测器相比，所提出的检测器在能量和面积效率方面具有竞争力，并且可以适应不同的通道条件和数量大规模 MIMO 系统中的用户。