Integrated Voltage Regulators (IVRs) are attractive substitutes for conventional voltage regulators located on the motherboards, due to outstanding dynamic performances and superior power densities. IVRs operate with switching frequencies in the range of $100\,{\rm MHz}$ and are assembled in highly compact packages close to the microprocessor load. This paper presents a comprehensive characterization of a PCB- and inductor-based four-phase ANPC-type IVR that uses a Power Management IC (PMIC) implemented in a $14\,{\rm nm}$ CMOS technology node. The characterization is based on the results of electrical measurements, thermal inspections of the chip surface, and simulations, which enables the separation of the total losses into on-chip and off-chip loss components and the allocation of important loss components inside the chip. The investigated IVR achieves a maximum efficiency of $84.1{\%}$ at an output power of $P_{\text{out}} = 640\,{\rm mW}$ and a switching frequency of $f_{\text s} = 50\,{\rm MHz}$ . The thermal measurements reveal that the maximum efficiency of the PMIC itself is between $88\,\%$ and $90\,\%$ at $f_{\text s} = 50\,{\rm MHz}$ and $P_{\text{out}} \in [500\,{\rm mW},\,600\,{\rm mW}]$ ; at $P_{\text{out}} = 890\,{\rm mW}$ , a chip current density of $24.7\,{\rm A/mm^2}$ is achieved. The findings in particular point out that the losses in the chip-internal interconnections, i.e., the conductors of the Power Distribution Network (PDN) and the twelve stacked metal layers below the PDN, have a substantial contribution to the total losses. Furthermore, the combination of Cadence post-layout simulations with impedance networks obtained from an appropriate software tool, e.g., FastHenry, is found to establish a suitable toolbox for estimating losses in IVRs.

中文翻译：

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基于电感的ANPC型Buck转换器在14 nm CMOS技术中的电气和热特性，适用于微处理器应用

集成式稳压器（IVR）具有出色的动态性能和出色的功率密度，是主板上常规稳压器的有吸引力的替代品。IVR的开关频率范围为$ 100 \，{\ rm MHz} $并以高度紧凑的封装组装，接近微处理器的负载。本文介绍了一个基于PCB和电感器的四相ANPC型IVR的全面特性，该IVR使用了在ADM中实现的电源管理IC（PMIC）。$ 14 \，{\ rm nm} $CMOS技术节点。表征基于电气测量，芯片表面热检查和仿真的结果，从而可以将总损耗分为芯片上和芯片外损耗成分，并在芯片内部分配重要的损耗成分。经调查的IVR的最大效率为$ 84.1 {\％} $ 在输出功率为 $ P _ {\ text {out}} = 640 \，{\ rm mW} $ 开关频率为 $ f _ {\ text s} = 50 \，{\ rm MHz} $ 。热测量表明，PMIC本身的最大效率介于$ 88 \，\％$ 和 $ 90 \，\％$ 在 $ f _ {\ text s} = 50 \，{\ rm MHz} $ 和 $ P _ {\ text {out}} \ in [500 \，{\ rm mW}，\，600 \，{\ rm mW}] $ ; 在$ P _ {\ text {out}} = 890 \，{\ rm mW} $ ，芯片电流密度为 $ 24.7 \，{\ rm A / mm ^ 2} $已完成。这些发现特别指出，芯片内部互连中的损耗（即配电网络（PDN）的导体和PDN下方的十二个堆叠金属层）对总损耗有重大贡献。此外，发现将Cadence布局后仿真与从合适的软件工具（例如FastHenry）获得的阻抗网络相结合，可以建立一个合适的工具箱来估算IVR中的损耗。